[binutils][aarch64] New iclass sve_size_hsd2.

Add "sve_size_hsd2" iclass decode that uses the new FLD_SVE_size field
value to determine the variant of an instruction.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_size_hsd2 iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_size_hsd2 iclass decode.
	* aarch64-opc.c (fields): Handle SVE_size field.
	* aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.

diff --git a/include/ChangeLog b/include/ChangeLog
index 14415ed90791b221964105dc6890bb085d54c650..cf24ee4e465cd0520a8be12666097f80f5fab20a 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.
+
 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 
        * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index e3924991f0b781571ca20633557bc68fd42daac7..a7a7459c5fb5a928399792ca38ed204683923f59 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -590,6 +590,7 @@ enum aarch64_insn_class
   sve_size_bhs,
   sve_size_bhsd,
   sve_size_hsd,
+  sve_size_hsd2,
   sve_size_sd,
   testbranch,
   cryptosm3,

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a1a842d225bb13a36af8721eba0f4854f9fcc861..8e8b185ea3959b67f1bdb43c3eadbc21a4288839 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,12 @@
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
+       sve_size_hsd2 iclass encode.
+       * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+       sve_size_hsd2 iclass decode.
+       * aarch64-opc.c (fields): Handle SVE_size field.
+       * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
+
 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 
        * aarch64-asm-2.c: Regenerated.

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 2424b66d9662718fb7a5475972ba57c9595954dd..d4f498f5ddc99aa7f7af3e49b44ec5233faa675a 100644 (file)
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1659,6 +1659,11 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
       insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0);
       break;
 
+    case sve_size_hsd2:
+      insert_field (FLD_SVE_size, &inst->value,
+                   aarch64_get_variant (inst) + 1, 0);
+      break;
+
     default:
       break;
     }

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index eea649fd3cc96059a1f23170c91cc1cfe75efac3..844c6ab68b2bfe8831478a9211a9da614f9e11d9 100644 (file)
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2810,6 +2810,13 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
       variant = extract_field (FLD_SVE_sz, inst->value, 0);
       break;
 
+    case sve_size_hsd2:
+      i = extract_field (FLD_SVE_size, inst->value, 0);
+      if (i < 1)
+       return FALSE;
+      variant = i - 1;
+      break;
+
     default:
       /* No mapping between instruction class and qualifiers.  */
       return TRUE;

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index eb3a1e400d148170a7b526eb14b10c737912e636..97cbfc8c2aaa4f067ad377343e45ee26cd1e47f8 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -311,6 +311,7 @@ const aarch64_field fields[] =
     { 10,  2 }, /* SVE_rot2: 2-bit rotation amount.  */
     { 10,  1 }, /* SVE_rot3: 1-bit rotation amount at bit 10.  */
     { 22,  1 }, /* SVE_sz: 1-bit element size select.  */
+    { 17,  2 }, /* SVE_size: 2-bit element size, bits [18,17].  */
     { 16,  4 }, /* SVE_tsz: triangular size select.  */
     { 22,  2 }, /* SVE_tszh: triangular size select high, bits [23,22].  */
     {  8,  2 }, /* SVE_tszl_8: triangular size select low, bits [9,8].  */

diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index b1060d459339b69fdf0fd77833effd4bc04bb809..942fa580f3d748b8aee9a568d90596016b23d5cd 100644 (file)
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -138,6 +138,7 @@ enum aarch64_field_kind
   FLD_SVE_rot2,
   FLD_SVE_rot3,
   FLD_SVE_sz,
+  FLD_SVE_size,
   FLD_SVE_tsz,
   FLD_SVE_tszh,
   FLD_SVE_tszl_8,