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Merge pull request #953 from YosysHQ/clifford/fix948
authorClifford Wolf <clifford@clifford.at>
Mon, 22 Apr 2019 18:01:09 +0000 (20:01 +0200)
committerGitHub <noreply@github.com>
Mon, 22 Apr 2019 18:01:09 +0000 (20:01 +0200)
Add support for zero-width signals to Verilog back-end


Trivial merge