Fix ordering of when to insert zero index

diff --git a/passes/techmap/pmux2shiftx.cc b/passes/techmap/pmux2shiftx.cc
index f8cdf578315b2bf00b5b7e965536e56bc544571c..6ffc27a4cb5c0a12f60e46ba86174a1d48d03150 100644 (file)
--- a/passes/techmap/pmux2shiftx.cc
+++ b/passes/techmap/pmux2shiftx.cc
@@ -65,8 +65,7 @@ struct Pmux2ShiftxPass : public Pass {
                        const int clog2width = ceil(log2(s_width));
 
                        RTLIL::SigSpec pmux_b;
-                       pmux_b.append(RTLIL::Const(0, clog2width));
-                       for (int i = s_width-1; i > 0; i--)
+                       for (int i = s_width-1; i >= 0; i--)
                                pmux_b.append(RTLIL::Const(i, clog2width));
                        shiftx_a.append(cell->getPort("\\B"));
                        pmux_s.append(cell->getPort("\\S"));