add slids

diff --git a/shakti/m_class/libre_riscv_chennai_2018.tex b/shakti/m_class/libre_riscv_chennai_2018.tex
index c4a56725e1746faf5bb2107e5c2b33d9f8ad4054..b5aae111ba615cb458c3ab63cb0bdcc129b3c951 100644 (file)
--- a/shakti/m_class/libre_riscv_chennai_2018.tex
+++ b/shakti/m_class/libre_riscv_chennai_2018.tex
@@ -285,18 +285,15 @@
 
  \begin{itemize}
    \item Been done before, but not as a Libre Design.
-          \vspace{4pt}
+   \item Sanjay Charagulla: GlobalFoundries, 22nm mobile process
+            can reach as low as 0.4v
    \item GPIO Banks need per-bank VREF (1.8v? to 3.3v)\\
              IO pads need built-in
             level-shifting to convert to CPU VCORE
-          \vspace{4pt}
    \item Each core needs independent variable-voltage capability
             and independent shut-down (PMIC supplies external voltage)
-          \vspace{4pt}
    \item DDR RAM still needs refreshing (even in sleep mode)
-          \vspace{4pt}
    \item Extra RV32 (PicoRV32?) always-on core for wake-up / RTC?
-          \vspace{4pt}
    \item PLLs are Analog.  fun fun fun in the sun sun sun...
   \end{itemize}
    {\it Really need help here.  PLLs, Analog stuff: very specific