Update cke => clk_en in test

diff --git a/gram/test/test_dfii.py b/gram/test/test_dfii.py
index 475e980f4057fc16d51b473f75a86f0a8902a959..6bb238e794a0a5412aeae0c5c5dd0b0991466df3 100644 (file)
--- a/gram/test/test_dfii.py
+++ b/gram/test/test_dfii.py
@@ -128,17 +128,17 @@ class DFIInjectorTestCase(FHDLTestCase):
 
         return (m, dut, csrhost)
 
-    def test_cke(self):
+    def test_clk_en(self):
         m, dut, csrhost = self.generate_dfiinjector()
 
         def process():
             yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, (1 << 1), sel=0xF)
             yield
-            self.assertTrue((yield dut.master.phases[0].cke[0]))
+            self.assertTrue((yield dut.master.phases[0].clk_en[0]))
 
             yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, 0, sel=0xF)
             yield
-            self.assertFalse((yield dut.master.phases[0].cke[0]))
+            self.assertFalse((yield dut.master.phases[0].clk_en[0]))
 
         runSimulation(m, process, "test_dfiinjector.vcd")