---------- Begin Simulation Statistics ----------
-sim_seconds 0.000667 # Number of seconds simulated
-sim_ticks 667407500 # Number of ticks simulated
-final_tick 667407500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 176952 # Simulator instruction rate (inst/s)
-host_op_rate 363878 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1763538835 # Simulator tick rate (ticks/s)
-host_mem_usage 1336256 # Number of bytes of host memory used
-host_seconds 0.38 # Real time elapsed on the host
-sim_insts 66963 # Number of instructions simulated
-sim_ops 137705 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::dir_cntrl0 99136 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 99136 # Number of bytes read from this memory
-system.mem_ctrls.num_reads::dir_cntrl0 1549 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 1549 # Number of read requests responded to by this memory
-system.mem_ctrls.bw_read::dir_cntrl0 148538936 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 148538936 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::dir_cntrl0 148538936 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 148538936 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 1549 # Number of read requests accepted
-system.mem_ctrls.writeReqs 0 # Number of write requests accepted
-system.mem_ctrls.readBursts 1549 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 99136 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 99136 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 91 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 52 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 42 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 54 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 56 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 174 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 90 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 222 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 125 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 51 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 94 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 667174000 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 1549 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 1540 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 2 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 484 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 203.371901 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 144.930715 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 194.713066 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 177 36.57% 36.57% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 168 34.71% 71.28% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 63 13.02% 84.30% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 29 5.99% 90.29% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 19 3.93% 94.21% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 11 2.27% 96.49% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 10 2.07% 98.55% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 2 0.41% 98.97% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 5 1.03% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 484 # Bytes accessed per row activation
-system.mem_ctrls.totQLat 31625750 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 60669500 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 7745000 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 20416.88 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 39166.88 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 148.54 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 148.54 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 1.16 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 1.16 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 1060 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 68.43 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 430712.72 # Average gap between requests
-system.mem_ctrls.pageHitRate 68.43 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 1320900 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 694485 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 4876620 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 51629760.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 18588840 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 1670400 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.actPowerDownEnergy 210561990 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_0.prePowerDownEnergy 42231360 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_0.selfRefreshEnergy 15446940 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_0.totalEnergy 347021295 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 519.954143 # Core power per rank (mW)
-system.mem_ctrls_0.totalIdleTime 622134250 # Total Idle time Per DRAM Rank
-system.mem_ctrls_0.memoryStateTime::IDLE 2030000 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 21876000 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::SREF 50557000 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 109975750 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 21192250 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 461776500 # Time in different power states
-system.mem_ctrls_1.actEnergy 2170560 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 1142295 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 6183240 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 52244400.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 21584190 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 1299360 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.actPowerDownEnergy 243510840 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_1.prePowerDownEnergy 28002720 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_1.selfRefreshEnergy 2892540 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_1.totalEnergy 359030145 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 537.947423 # Core power per rank (mW)
-system.mem_ctrls_1.totalIdleTime 616133750 # Total Idle time Per DRAM Rank
-system.mem_ctrls_1.memoryStateTime::IDLE 980000 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 22106000 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::SREF 9751250 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 72913500 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 27618000 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 534038750 # Time in different power states
-system.ruby.clk_domain.clock 500 # Clock period in ticks
-system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 2856 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 2856 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_read::total 822304 # Number of bytes read from this memory
-system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory
-system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 1576 # Number of instructions bytes read from this memory
-system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 1576 # Number of instructions bytes read from this memory
-system.ruby.phys_mem.bytes_inst_read::total 699912 # Number of instructions bytes read from this memory
-system.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory
-system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory
-system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory
-system.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory
-system.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 547 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 547 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_reads::total 104875 # Number of read requests responded to by this memory
-system.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory
-system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory
-system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory
-system.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory
-system.ruby.phys_mem.bw_read::cpu0.inst 1043979877 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::cpu0.data 179548477 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4279245 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4279245 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_read::total 1232086843 # Total read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::cpu0.inst 1043979877 # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 2361376 # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 2361376 # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_inst_read::total 1048702629 # Instruction read bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::cpu0.data 109029341 # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 383574 # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 383574 # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_write::total 109796489 # Write bandwidth from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu0.inst 1043979877 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu0.data 288577818 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 4662818 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 4662818 # Total bandwidth to/from this memory (bytes/s)
-system.ruby.phys_mem.bw_total::total 1341883332 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.ruby.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
+sim_seconds 0.000667
+sim_ticks 667407500
+final_tick 667407500
+sim_freq 1000000000000
+host_inst_rate 219740
+host_op_rate 451865
+host_tick_rate 2189959227
+host_mem_usage 1336836
+host_seconds 0.30
+sim_insts 66963
+sim_ops 137705
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 667407500
+system.mem_ctrls.bytes_read::dir_cntrl0 99136
+system.mem_ctrls.bytes_read::total 99136
+system.mem_ctrls.num_reads::dir_cntrl0 1549
+system.mem_ctrls.num_reads::total 1549
+system.mem_ctrls.bw_read::dir_cntrl0 148538936
+system.mem_ctrls.bw_read::total 148538936
+system.mem_ctrls.bw_total::dir_cntrl0 148538936
+system.mem_ctrls.bw_total::total 148538936
+system.mem_ctrls.readReqs 1549
+system.mem_ctrls.writeReqs 0
+system.mem_ctrls.readBursts 1549
+system.mem_ctrls.writeBursts 0
+system.mem_ctrls.bytesReadDRAM 99136
+system.mem_ctrls.bytesReadWrQ 0
+system.mem_ctrls.bytesWritten 0
+system.mem_ctrls.bytesReadSys 99136
+system.mem_ctrls.bytesWrittenSys 0
+system.mem_ctrls.servicedByWrQ 0
+system.mem_ctrls.mergedWrBursts 0
+system.mem_ctrls.neitherReadNorWriteReqs 0
+system.mem_ctrls.perBankRdBursts::0 122
+system.mem_ctrls.perBankRdBursts::1 192
+system.mem_ctrls.perBankRdBursts::2 91
+system.mem_ctrls.perBankRdBursts::3 44
+system.mem_ctrls.perBankRdBursts::4 61
+system.mem_ctrls.perBankRdBursts::5 79
+system.mem_ctrls.perBankRdBursts::6 52
+system.mem_ctrls.perBankRdBursts::7 42
+system.mem_ctrls.perBankRdBursts::8 54
+system.mem_ctrls.perBankRdBursts::9 56
+system.mem_ctrls.perBankRdBursts::10 174
+system.mem_ctrls.perBankRdBursts::11 90
+system.mem_ctrls.perBankRdBursts::12 222
+system.mem_ctrls.perBankRdBursts::13 125
+system.mem_ctrls.perBankRdBursts::14 51
+system.mem_ctrls.perBankRdBursts::15 94
+system.mem_ctrls.perBankWrBursts::0 0
+system.mem_ctrls.perBankWrBursts::1 0
+system.mem_ctrls.perBankWrBursts::2 0
+system.mem_ctrls.perBankWrBursts::3 0
+system.mem_ctrls.perBankWrBursts::4 0
+system.mem_ctrls.perBankWrBursts::5 0
+system.mem_ctrls.perBankWrBursts::6 0
+system.mem_ctrls.perBankWrBursts::7 0
+system.mem_ctrls.perBankWrBursts::8 0
+system.mem_ctrls.perBankWrBursts::9 0
+system.mem_ctrls.perBankWrBursts::10 0
+system.mem_ctrls.perBankWrBursts::11 0
+system.mem_ctrls.perBankWrBursts::12 0
+system.mem_ctrls.perBankWrBursts::13 0
+system.mem_ctrls.perBankWrBursts::14 0
+system.mem_ctrls.perBankWrBursts::15 0
+system.mem_ctrls.numRdRetry 0
+system.mem_ctrls.numWrRetry 0
+system.mem_ctrls.totGap 667174000
+system.mem_ctrls.readPktSize::0 0
+system.mem_ctrls.readPktSize::1 0
+system.mem_ctrls.readPktSize::2 0
+system.mem_ctrls.readPktSize::3 0
+system.mem_ctrls.readPktSize::4 0
+system.mem_ctrls.readPktSize::5 0
+system.mem_ctrls.readPktSize::6 1549
+system.mem_ctrls.writePktSize::0 0
+system.mem_ctrls.writePktSize::1 0
+system.mem_ctrls.writePktSize::2 0
+system.mem_ctrls.writePktSize::3 0
+system.mem_ctrls.writePktSize::4 0
+system.mem_ctrls.writePktSize::5 0
+system.mem_ctrls.writePktSize::6 0
+system.mem_ctrls.rdQLenPdf::0 1540
+system.mem_ctrls.rdQLenPdf::1 2
+system.mem_ctrls.rdQLenPdf::2 1
+system.mem_ctrls.rdQLenPdf::3 1
+system.mem_ctrls.rdQLenPdf::4 2
+system.mem_ctrls.rdQLenPdf::5 1
+system.mem_ctrls.rdQLenPdf::6 1
+system.mem_ctrls.rdQLenPdf::7 1
+system.mem_ctrls.rdQLenPdf::8 0
+system.mem_ctrls.rdQLenPdf::9 0
+system.mem_ctrls.rdQLenPdf::10 0
+system.mem_ctrls.rdQLenPdf::11 0
+system.mem_ctrls.rdQLenPdf::12 0
+system.mem_ctrls.rdQLenPdf::13 0
+system.mem_ctrls.rdQLenPdf::14 0
+system.mem_ctrls.rdQLenPdf::15 0
+system.mem_ctrls.rdQLenPdf::16 0
+system.mem_ctrls.rdQLenPdf::17 0
+system.mem_ctrls.rdQLenPdf::18 0
+system.mem_ctrls.rdQLenPdf::19 0
+system.mem_ctrls.rdQLenPdf::20 0
+system.mem_ctrls.rdQLenPdf::21 0
+system.mem_ctrls.rdQLenPdf::22 0
+system.mem_ctrls.rdQLenPdf::23 0
+system.mem_ctrls.rdQLenPdf::24 0
+system.mem_ctrls.rdQLenPdf::25 0
+system.mem_ctrls.rdQLenPdf::26 0
+system.mem_ctrls.rdQLenPdf::27 0
+system.mem_ctrls.rdQLenPdf::28 0
+system.mem_ctrls.rdQLenPdf::29 0
+system.mem_ctrls.rdQLenPdf::30 0
+system.mem_ctrls.rdQLenPdf::31 0
+system.mem_ctrls.wrQLenPdf::0 0
+system.mem_ctrls.wrQLenPdf::1 0
+system.mem_ctrls.wrQLenPdf::2 0
+system.mem_ctrls.wrQLenPdf::3 0
+system.mem_ctrls.wrQLenPdf::4 0
+system.mem_ctrls.wrQLenPdf::5 0
+system.mem_ctrls.wrQLenPdf::6 0
+system.mem_ctrls.wrQLenPdf::7 0
+system.mem_ctrls.wrQLenPdf::8 0
+system.mem_ctrls.wrQLenPdf::9 0
+system.mem_ctrls.wrQLenPdf::10 0
+system.mem_ctrls.wrQLenPdf::11 0
+system.mem_ctrls.wrQLenPdf::12 0
+system.mem_ctrls.wrQLenPdf::13 0
+system.mem_ctrls.wrQLenPdf::14 0
+system.mem_ctrls.wrQLenPdf::15 0
+system.mem_ctrls.wrQLenPdf::16 0
+system.mem_ctrls.wrQLenPdf::17 0
+system.mem_ctrls.wrQLenPdf::18 0
+system.mem_ctrls.wrQLenPdf::19 0
+system.mem_ctrls.wrQLenPdf::20 0
+system.mem_ctrls.wrQLenPdf::21 0
+system.mem_ctrls.wrQLenPdf::22 0
+system.mem_ctrls.wrQLenPdf::23 0
+system.mem_ctrls.wrQLenPdf::24 0
+system.mem_ctrls.wrQLenPdf::25 0
+system.mem_ctrls.wrQLenPdf::26 0
+system.mem_ctrls.wrQLenPdf::27 0
+system.mem_ctrls.wrQLenPdf::28 0
+system.mem_ctrls.wrQLenPdf::29 0
+system.mem_ctrls.wrQLenPdf::30 0
+system.mem_ctrls.wrQLenPdf::31 0
+system.mem_ctrls.wrQLenPdf::32 0
+system.mem_ctrls.wrQLenPdf::33 0
+system.mem_ctrls.wrQLenPdf::34 0
+system.mem_ctrls.wrQLenPdf::35 0
+system.mem_ctrls.wrQLenPdf::36 0
+system.mem_ctrls.wrQLenPdf::37 0
+system.mem_ctrls.wrQLenPdf::38 0
+system.mem_ctrls.wrQLenPdf::39 0
+system.mem_ctrls.wrQLenPdf::40 0
+system.mem_ctrls.wrQLenPdf::41 0
+system.mem_ctrls.wrQLenPdf::42 0
+system.mem_ctrls.wrQLenPdf::43 0
+system.mem_ctrls.wrQLenPdf::44 0
+system.mem_ctrls.wrQLenPdf::45 0
+system.mem_ctrls.wrQLenPdf::46 0
+system.mem_ctrls.wrQLenPdf::47 0
+system.mem_ctrls.wrQLenPdf::48 0
+system.mem_ctrls.wrQLenPdf::49 0
+system.mem_ctrls.wrQLenPdf::50 0
+system.mem_ctrls.wrQLenPdf::51 0
+system.mem_ctrls.wrQLenPdf::52 0
+system.mem_ctrls.wrQLenPdf::53 0
+system.mem_ctrls.wrQLenPdf::54 0
+system.mem_ctrls.wrQLenPdf::55 0
+system.mem_ctrls.wrQLenPdf::56 0
+system.mem_ctrls.wrQLenPdf::57 0
+system.mem_ctrls.wrQLenPdf::58 0
+system.mem_ctrls.wrQLenPdf::59 0
+system.mem_ctrls.wrQLenPdf::60 0
+system.mem_ctrls.wrQLenPdf::61 0
+system.mem_ctrls.wrQLenPdf::62 0
+system.mem_ctrls.wrQLenPdf::63 0
+system.mem_ctrls.bytesPerActivate::samples 484
+system.mem_ctrls.bytesPerActivate::mean 203.371901
+system.mem_ctrls.bytesPerActivate::gmean 144.930715
+system.mem_ctrls.bytesPerActivate::stdev 194.713066
+system.mem_ctrls.bytesPerActivate::0-127 177 36.57% 36.57%
+system.mem_ctrls.bytesPerActivate::128-255 168 34.71% 71.28%
+system.mem_ctrls.bytesPerActivate::256-383 63 13.02% 84.30%
+system.mem_ctrls.bytesPerActivate::384-511 29 5.99% 90.29%
+system.mem_ctrls.bytesPerActivate::512-639 19 3.93% 94.21%
+system.mem_ctrls.bytesPerActivate::640-767 11 2.27% 96.49%
+system.mem_ctrls.bytesPerActivate::768-895 10 2.07% 98.55%
+system.mem_ctrls.bytesPerActivate::896-1023 2 0.41% 98.97%
+system.mem_ctrls.bytesPerActivate::1024-1151 5 1.03% 100.00%
+system.mem_ctrls.bytesPerActivate::total 484
+system.mem_ctrls.totQLat 31625750
+system.mem_ctrls.totMemAccLat 60669500
+system.mem_ctrls.totBusLat 7745000
+system.mem_ctrls.avgQLat 20416.88
+system.mem_ctrls.avgBusLat 5000.00
+system.mem_ctrls.avgMemAccLat 39166.88
+system.mem_ctrls.avgRdBW 148.54
+system.mem_ctrls.avgWrBW 0.00
+system.mem_ctrls.avgRdBWSys 148.54
+system.mem_ctrls.avgWrBWSys 0.00
+system.mem_ctrls.peakBW 12800.00
+system.mem_ctrls.busUtil 1.16
+system.mem_ctrls.busUtilRead 1.16
+system.mem_ctrls.busUtilWrite 0.00
+system.mem_ctrls.avgRdQLen 1.00
+system.mem_ctrls.avgWrQLen 0.00
+system.mem_ctrls.readRowHits 1060
+system.mem_ctrls.writeRowHits 0
+system.mem_ctrls.readRowHitRate 68.43
+system.mem_ctrls.writeRowHitRate nan
+system.mem_ctrls.avgGap 430712.72
+system.mem_ctrls.pageHitRate 68.43
+system.mem_ctrls_0.actEnergy 1320900
+system.mem_ctrls_0.preEnergy 694485
+system.mem_ctrls_0.readEnergy 4876620
+system.mem_ctrls_0.writeEnergy 0
+system.mem_ctrls_0.refreshEnergy 51629760.000000
+system.mem_ctrls_0.actBackEnergy 18588840
+system.mem_ctrls_0.preBackEnergy 1670400
+system.mem_ctrls_0.actPowerDownEnergy 210561990
+system.mem_ctrls_0.prePowerDownEnergy 42231360
+system.mem_ctrls_0.selfRefreshEnergy 15446940
+system.mem_ctrls_0.totalEnergy 347021295
+system.mem_ctrls_0.averagePower 519.954143
+system.mem_ctrls_0.totalIdleTime 622134250
+system.mem_ctrls_0.memoryStateTime::IDLE 2030000
+system.mem_ctrls_0.memoryStateTime::REF 21876000
+system.mem_ctrls_0.memoryStateTime::SREF 50557000
+system.mem_ctrls_0.memoryStateTime::PRE_PDN 109975750
+system.mem_ctrls_0.memoryStateTime::ACT 21192250
+system.mem_ctrls_0.memoryStateTime::ACT_PDN 461776500
+system.mem_ctrls_1.actEnergy 2170560
+system.mem_ctrls_1.preEnergy 1142295
+system.mem_ctrls_1.readEnergy 6183240
+system.mem_ctrls_1.writeEnergy 0
+system.mem_ctrls_1.refreshEnergy 52244400.000000
+system.mem_ctrls_1.actBackEnergy 21584190
+system.mem_ctrls_1.preBackEnergy 1299360
+system.mem_ctrls_1.actPowerDownEnergy 243510840
+system.mem_ctrls_1.prePowerDownEnergy 28002720
+system.mem_ctrls_1.selfRefreshEnergy 2892540
+system.mem_ctrls_1.totalEnergy 359030145
+system.mem_ctrls_1.averagePower 537.947423
+system.mem_ctrls_1.totalIdleTime 616133750
+system.mem_ctrls_1.memoryStateTime::IDLE 980000
+system.mem_ctrls_1.memoryStateTime::REF 22106000
+system.mem_ctrls_1.memoryStateTime::SREF 9751250
+system.mem_ctrls_1.memoryStateTime::PRE_PDN 72913500
+system.mem_ctrls_1.memoryStateTime::ACT 27618000
+system.mem_ctrls_1.memoryStateTime::ACT_PDN 534038750
+system.ruby.clk_domain.clock 500
+system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 667407500
+system.ruby.phys_mem.bytes_read::cpu0.inst 696760
+system.ruby.phys_mem.bytes_read::cpu0.data 119832
+system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 2856
+system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 2856
+system.ruby.phys_mem.bytes_read::total 822304
+system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760
+system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 1576
+system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 1576
+system.ruby.phys_mem.bytes_inst_read::total 699912
+system.ruby.phys_mem.bytes_written::cpu0.data 72767
+system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256
+system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256
+system.ruby.phys_mem.bytes_written::total 73279
+system.ruby.phys_mem.num_reads::cpu0.inst 87095
+system.ruby.phys_mem.num_reads::cpu0.data 16686
+system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 547
+system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 547
+system.ruby.phys_mem.num_reads::total 104875
+system.ruby.phys_mem.num_writes::cpu0.data 10422
+system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256
+system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256
+system.ruby.phys_mem.num_writes::total 10934
+system.ruby.phys_mem.bw_read::cpu0.inst 1043979877
+system.ruby.phys_mem.bw_read::cpu0.data 179548477
+system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4279245
+system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4279245
+system.ruby.phys_mem.bw_read::total 1232086843
+system.ruby.phys_mem.bw_inst_read::cpu0.inst 1043979877
+system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 2361376
+system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 2361376
+system.ruby.phys_mem.bw_inst_read::total 1048702629
+system.ruby.phys_mem.bw_write::cpu0.data 109029341
+system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 383574
+system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 383574
+system.ruby.phys_mem.bw_write::total 109796489
+system.ruby.phys_mem.bw_total::cpu0.inst 1043979877
+system.ruby.phys_mem.bw_total::cpu0.data 288577818
+system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 4662818
+system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 4662818
+system.ruby.phys_mem.bw_total::total 1341883332
+system.pwrStateResidencyTicks::UNDEFINED 667407500
+system.ruby.pwrStateResidencyTicks::UNDEFINED 667407500
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 114203
system.ruby.miss_latency_hist_coalsr::total 27
system.ruby.L1Cache.incomplete_times_seqr 112609
system.ruby.L2Cache.incomplete_times_seqr 59
-system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits
-system.cp_cntrl0.L1D0cache.demand_misses 506 # Number of cache demand misses
-system.cp_cntrl0.L1D0cache.demand_accesses 506 # Number of cache demand accesses
-system.cp_cntrl0.L1D0cache.num_data_array_reads 16155 # number of data array reads
-system.cp_cntrl0.L1D0cache.num_data_array_writes 11985 # number of data array writes
-system.cp_cntrl0.L1D0cache.num_tag_array_reads 27132 # number of tag array reads
-system.cp_cntrl0.L1D0cache.num_tag_array_writes 1584 # number of tag array writes
-system.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits
-system.cp_cntrl0.L1D1cache.demand_misses 0 # Number of cache demand misses
-system.cp_cntrl0.L1D1cache.demand_accesses 0 # Number of cache demand accesses
-system.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
-system.cp_cntrl0.L1Icache.demand_misses 1088 # Number of cache demand misses
-system.cp_cntrl0.L1Icache.demand_accesses 1088 # Number of cache demand accesses
-system.cp_cntrl0.L1Icache.num_data_array_reads 86007 # number of data array reads
-system.cp_cntrl0.L1Icache.num_data_array_writes 54 # number of data array writes
-system.cp_cntrl0.L1Icache.num_tag_array_reads 87684 # number of tag array reads
-system.cp_cntrl0.L1Icache.num_tag_array_writes 54 # number of tag array writes
-system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
-system.cp_cntrl0.L2cache.demand_misses 1535 # Number of cache demand misses
-system.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses
-system.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads
-system.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes
-system.cp_cntrl0.L2cache.num_tag_array_reads 12057 # number of tag array reads
-system.cp_cntrl0.L2cache.num_tag_array_writes 1649 # number of tag array writes
-system.cp_cntrl0.mandatoryQueue.avg_buf_msgs 0.427713 # Average number of messages in buffer
-system.cp_cntrl0.mandatoryQueue.avg_stall_time 1999.994007 # Average number of cycles messages are stalled in this MB
-system.cp_cntrl0.probeToCore.avg_buf_msgs 0.000010 # Average number of messages in buffer
-system.cp_cntrl0.probeToCore.avg_stall_time 3665.454806 # Average number of cycles messages are stalled in this MB
-system.cp_cntrl0.requestFromCore.avg_buf_msgs 0.034499 # Average number of messages in buffer
-system.cp_cntrl0.requestFromCore.avg_stall_time 14999.617925 # Average number of cycles messages are stalled in this MB
-system.cp_cntrl0.responseFromCore.avg_buf_msgs 0.000315 # Average number of messages in buffer
-system.cp_cntrl0.responseFromCore.avg_stall_time 1717.844815 # Average number of cycles messages are stalled in this MB
-system.cp_cntrl0.responseToCore.avg_buf_msgs 0.001150 # Average number of messages in buffer
-system.cp_cntrl0.responseToCore.avg_stall_time 31990.122976 # Average number of cycles messages are stalled in this MB
-system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.cp_cntrl0.triggerQueue.avg_buf_msgs 0.001591 # Average number of messages in buffer
-system.cp_cntrl0.triggerQueue.avg_stall_time 15959.959998 # Average number of cycles messages are stalled in this MB
-system.cp_cntrl0.unblockFromCore.avg_buf_msgs 0.034499 # Average number of messages in buffer
-system.cp_cntrl0.unblockFromCore.avg_stall_time 14995.033020 # Average number of cycles messages are stalled in this MB
-system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.cpu0.clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.cpu0.workload.numSyscalls 21 # Number of system calls
-system.cpu0.numPwrStateTransitions 2 # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples 1 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean 2095501 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10 1 100.00% 100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value 2095501 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 2095501 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total 1 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON 665311999 # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 2095501 # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles 1334815 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 66963 # Number of instructions committed
-system.cpu0.committedOps 137705 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses
-system.cpu0.num_func_calls 3196 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 136380 # number of integer instructions
-system.cpu0.num_fp_insts 1279 # number of float instructions
-system.cpu0.num_int_register_reads 257490 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 110039 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 981 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written
-system.cpu0.num_mem_refs 27198 # number of memory refs
-system.cpu0.num_load_insts 16684 # Number of load instructions
-system.cpu0.num_store_insts 10514 # Number of store instructions
-system.cpu0.num_idle_cycles 4191.003994 # Number of idle cycles
-system.cpu0.num_busy_cycles 1330623.996006 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.996860 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.003140 # Percentage of idle cycles
-system.cpu0.Branches 16199 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction
-system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction
-system.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction
-system.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatMultAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatMisc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction
-system.cpu0.op_class::MemRead 16382 11.90% 92.15% # Class of executed instruction
-system.cpu0.op_class::MemWrite 10514 7.64% 99.78% # Class of executed instruction
-system.cpu0.op_class::FloatMemRead 302 0.22% 100.00% # Class of executed instruction
-system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 137705 # Class of executed instruction
-system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.cpu1.clk_domain.clock 1000 # Clock period in ticks
-system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 309 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 284 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 279 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 274 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 35 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 11.257143 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 5.595917 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 4 11.43% 11.43% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 4 11.43% 22.86% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.86% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 4 11.43% 37.14% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 4 11.43% 48.57% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 1 2.86% 51.43% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 51.43% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 17 48.57% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 16 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 35 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 2741 # number of cycles the CU issues nothing
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 625 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 340 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 338 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 335 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs0.ExecStage.spc::samples 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::mean 0.049648 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::stdev 0.277106 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::0 2741 96.51% 96.51% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::1 57 2.01% 98.52% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::2 42 1.48% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::3 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::max_value 2 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.spc::total 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 90 # number of CU transitions from active to idle
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 90 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 29.322222 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 145.995831 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 76 84.44% 84.44% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.78% 92.22% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 92.22% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 92.22% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 0 0.00% 92.22% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.11% 93.33% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 93.33% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 93.33% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 93.33% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 93.33% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 93.33% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 93.33% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 93.33% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 93.33% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 93.33% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 93.33% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 6 6.67% 100.00% # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1291 # duration of idle periods in cycles
-system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 90 # duration of idle periods in cycles
-system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF
-system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF
-system.cpu1.CUs0.valu_insts 68 # Number of vector ALU insts issued.
-system.cpu1.CUs0.valu_insts_per_wf 17 # The avg. number of vector ALU insts issued per-wavefront.
-system.cpu1.CUs0.salu_insts 0 # Number of scalar ALU insts issued.
-system.cpu1.CUs0.salu_insts_per_wf 0 # The avg. number of scalar ALU insts issued per-wavefront.
-system.cpu1.CUs0.inst_cycles_valu 68 # Number of cycles needed to execute VALU insts.
-system.cpu1.CUs0.inst_cycles_salu 0 # Number of cycles needed to execute SALU insts.
-system.cpu1.CUs0.thread_cycles_valu 3076 # Number of thread cycles used to execute vector ALU ops. Similar to instCyclesVALU but multiplied by the number of active threads.
-system.cpu1.CUs0.valu_utilization 70.680147 # Percentage of active vector ALU threads in a wave.
-system.cpu1.CUs0.lds_no_flat_insts 6 # Number of LDS insts issued, not including FLAT accesses that resolve to LDS.
-system.cpu1.CUs0.lds_no_flat_insts_per_wf 1.500000 # The avg. number of LDS insts (not including FLAT accesses that resolve to LDS) per-wavefront.
-system.cpu1.CUs0.flat_vmem_insts 0 # The number of FLAT insts that resolve to vmem issued.
-system.cpu1.CUs0.flat_vmem_insts_per_wf 0 # The average number of FLAT insts that resolve to vmem issued per-wavefront.
-system.cpu1.CUs0.flat_lds_insts 0 # The number of FLAT insts that resolve to LDS issued.
-system.cpu1.CUs0.flat_lds_insts_per_wf 0 # The average number of FLAT insts that resolve to LDS issued per-wavefront.
-system.cpu1.CUs0.vector_mem_writes 8 # Number of vector mem write insts (excluding FLAT insts).
-system.cpu1.CUs0.vector_mem_writes_per_wf 2 # The average number of vector mem write insts (excluding FLAT insts) per-wavefront.
-system.cpu1.CUs0.vector_mem_reads 29 # Number of vector mem read insts (excluding FLAT insts).
-system.cpu1.CUs0.vector_mem_reads_per_wf 7.250000 # The avg. number of vector mem read insts (excluding FLAT insts) per-wavefront.
-system.cpu1.CUs0.scalar_mem_writes 0 # Number of scalar mem write insts.
-system.cpu1.CUs0.scalar_mem_writes_per_wf 0 # The average number of scalar mem write insts per-wavefront.
-system.cpu1.CUs0.scalar_mem_reads 0 # Number of scalar mem read insts.
-system.cpu1.CUs0.scalar_mem_reads_per_wf 0 # The average number of scalar mem read insts per-wavefront.
-system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests
-system.cpu1.CUs0.tlb_cycles -454892896000 # total number of cycles for all uncoalesced requests
-system.cpu1.CUs0.avg_translation_latency -591538226.267880 # Avg. translation latency for data translations
-system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses
-system.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::10-11 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::12-13 4 66.67% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs0.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count
-system.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count
-system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity
-system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed
-system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::mean 71.028369 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::stdev 225.061514 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 8.51% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::4-5 61 43.26% 51.77% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::6-7 32 22.70% 74.47% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 76.60% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 78.72% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::overflows 30 21.28% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::max_value 1297 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. WF size/inst)
-system.cpu1.CUs0.num_total_cycles 2840 # number of cycles the CU ran for
-system.cpu1.CUs0.vpc 2.383451 # Vector Operations per cycle (this CU only)
-system.cpu1.CUs0.ipc 0.049648 # Instructions per cycle (this CU only)
-system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs0.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::mean 37.833333 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::stdev 27.064737 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::9-12 0 0.00% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::13-16 8 44.44% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction
-system.cpu1.CUs0.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::mean 19.500000 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::stdev 22.322634 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::9-12 0 0.00% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::13-16 4 66.67% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction
-system.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction
-system.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed
-system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD
-system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations
-system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed
-system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts
-system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 406 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 381 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 372 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 364 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
-system.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
-system.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
-system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 35 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 11.257143 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 5.595917 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 4 11.43% 11.43% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 4 11.43% 22.86% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.86% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 4 11.43% 37.14% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 4 11.43% 48.57% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 1 2.86% 51.43% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 51.43% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 17 48.57% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 16 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 35 # For each instruction fetch request recieved record how many instructions you got from it
-system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 2740 # number of cycles the CU issues nothing
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 100 # number of cycles the CU issued at least one instruction
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 795 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 437 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 431 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 422 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 408 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued
-system.cpu1.CUs1.ExecStage.spc::samples 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::mean 0.049648 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::stdev 0.275831 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::0 2740 96.48% 96.48% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::1 59 2.08% 98.56% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::2 41 1.44% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::3 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::max_value 2 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.spc::total 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe)
-system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 91 # number of CU transitions from active to idle
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 91 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 30.010989 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 148.108031 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 76 83.52% 83.52% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.79% 92.31% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 92.31% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 92.31% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 0 0.00% 92.31% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.10% 93.41% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 93.41% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 93.41% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 93.41% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 93.41% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 93.41% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 93.41% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 93.41% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 93.41% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 93.41% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 93.41% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 6 6.59% 100.00% # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1299 # duration of idle periods in cycles
-system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 91 # duration of idle periods in cycles
-system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF
-system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF
-system.cpu1.CUs1.valu_insts 68 # Number of vector ALU insts issued.
-system.cpu1.CUs1.valu_insts_per_wf 17 # The avg. number of vector ALU insts issued per-wavefront.
-system.cpu1.CUs1.salu_insts 0 # Number of scalar ALU insts issued.
-system.cpu1.CUs1.salu_insts_per_wf 0 # The avg. number of scalar ALU insts issued per-wavefront.
-system.cpu1.CUs1.inst_cycles_valu 68 # Number of cycles needed to execute VALU insts.
-system.cpu1.CUs1.inst_cycles_salu 0 # Number of cycles needed to execute SALU insts.
-system.cpu1.CUs1.thread_cycles_valu 3071 # Number of thread cycles used to execute vector ALU ops. Similar to instCyclesVALU but multiplied by the number of active threads.
-system.cpu1.CUs1.valu_utilization 70.565257 # Percentage of active vector ALU threads in a wave.
-system.cpu1.CUs1.lds_no_flat_insts 6 # Number of LDS insts issued, not including FLAT accesses that resolve to LDS.
-system.cpu1.CUs1.lds_no_flat_insts_per_wf 1.500000 # The avg. number of LDS insts (not including FLAT accesses that resolve to LDS) per-wavefront.
-system.cpu1.CUs1.flat_vmem_insts 0 # The number of FLAT insts that resolve to vmem issued.
-system.cpu1.CUs1.flat_vmem_insts_per_wf 0 # The average number of FLAT insts that resolve to vmem issued per-wavefront.
-system.cpu1.CUs1.flat_lds_insts 0 # The number of FLAT insts that resolve to LDS issued.
-system.cpu1.CUs1.flat_lds_insts_per_wf 0 # The average number of FLAT insts that resolve to LDS issued per-wavefront.
-system.cpu1.CUs1.vector_mem_writes 8 # Number of vector mem write insts (excluding FLAT insts).
-system.cpu1.CUs1.vector_mem_writes_per_wf 2 # The average number of vector mem write insts (excluding FLAT insts) per-wavefront.
-system.cpu1.CUs1.vector_mem_reads 29 # Number of vector mem read insts (excluding FLAT insts).
-system.cpu1.CUs1.vector_mem_reads_per_wf 7.250000 # The avg. number of vector mem read insts (excluding FLAT insts) per-wavefront.
-system.cpu1.CUs1.scalar_mem_writes 0 # Number of scalar mem write insts.
-system.cpu1.CUs1.scalar_mem_writes_per_wf 0 # The average number of scalar mem write insts per-wavefront.
-system.cpu1.CUs1.scalar_mem_reads 0 # Number of scalar mem read insts.
-system.cpu1.CUs1.scalar_mem_reads_per_wf 0 # The average number of scalar mem read insts per-wavefront.
-system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests
-system.cpu1.CUs1.tlb_cycles -454919630000 # total number of cycles for all uncoalesced requests
-system.cpu1.CUs1.avg_translation_latency -591572990.897269 # Avg. translation latency for data translations
-system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB
-system.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses
-system.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::10-11 1 16.67% 50.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::12-13 3 50.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet
-system.cpu1.CUs1.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.)
-system.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count
-system.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count
-system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity
-system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed
-system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::mean 72.113475 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::stdev 228.065470 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::2-3 13 9.22% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::4-5 60 42.55% 51.77% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::6-7 34 24.11% 75.89% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::8-9 3 2.13% 78.01% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::10 1 0.71% 78.72% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::overflows 30 21.28% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::max_value 1305 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle
-system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. WF size/inst)
-system.cpu1.CUs1.num_total_cycles 2840 # number of cycles the CU ran for
-system.cpu1.CUs1.vpc 2.380986 # Vector Operations per cycle (this CU only)
-system.cpu1.CUs1.ipc 0.049648 # Instructions per cycle (this CU only)
-system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions)
-system.cpu1.CUs1.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::mean 37.722222 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::stdev 27.174394 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::9-12 2 11.11% 16.67% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::13-16 6 33.33% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction
-system.cpu1.CUs1.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::mean 19.333333 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::stdev 22.384518 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::9-12 1 16.67% 33.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::13-16 3 50.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction
-system.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction
-system.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed
-system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD
-system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations
-system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed
-system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts
-system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.cpu2.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.cpu2.num_kernel_launched 1 # number of kernel launched
-system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits
-system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses
-system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses
-system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1549 # number of data array writes
-system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1549 # number of tag array reads
-system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1549 # number of tag array writes
-system.dir_cntrl0.probeToCore.avg_buf_msgs 0.069628 # Average number of messages in buffer
-system.dir_cntrl0.probeToCore.avg_stall_time 29997.797448 # Average number of cycles messages are stalled in this MB
-system.dir_cntrl0.requestFromCores.avg_buf_msgs 0.001160 # Average number of messages in buffer
-system.dir_cntrl0.requestFromCores.avg_stall_time 17271.531260 # Average number of cycles messages are stalled in this MB
-system.dir_cntrl0.responseFromCores.avg_buf_msgs 0.001160 # Average number of messages in buffer
-system.dir_cntrl0.responseFromCores.avg_stall_time 121679.841776 # Average number of cycles messages are stalled in this MB
-system.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.003110 # Average number of messages in buffer
-system.dir_cntrl0.responseFromMemory.avg_stall_time 999.889123 # Average number of cycles messages are stalled in this MB
-system.dir_cntrl0.responseToCore.avg_buf_msgs 0.069628 # Average number of messages in buffer
-system.dir_cntrl0.responseToCore.avg_stall_time 29990.830190 # Average number of cycles messages are stalled in this MB
-system.dir_cntrl0.triggerQueue.avg_buf_msgs 0.002321 # Average number of messages in buffer
-system.dir_cntrl0.triggerQueue.avg_stall_time 999.739290 # Average number of cycles messages are stalled in this MB
-system.dir_cntrl0.unblockFromCores.avg_buf_msgs 0.001160 # Average number of messages in buffer
-system.dir_cntrl0.unblockFromCores.avg_stall_time 17249.343916 # Average number of cycles messages are stalled in this MB
-system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks
-system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses
-system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses
-system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue
-system.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts
-system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks
-system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses
-system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits
-system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses
-system.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate
-system.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses
-system.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits
-system.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses
-system.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate
-system.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level
-system.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table
-system.dispatcher_tlb.unique_pages 0 # Number of unique pages touched
-system.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs
-system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks
-system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses
-system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses
-system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue
-system.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts
-system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks
-system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses
-system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses
-system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue
-system.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts
-system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks
-system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses
-system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits
-system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses
-system.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate
-system.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses
-system.l1_tlb0.global_TLB_hits 774 # Number of TLB hits
-system.l1_tlb0.global_TLB_misses 4 # Number of TLB misses
-system.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate
-system.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level
-system.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table
-system.l1_tlb0.unique_pages 4 # Number of unique pages touched
-system.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs
-system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks
-system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses
-system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits
-system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses
-system.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate
-system.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses
-system.l1_tlb1.global_TLB_hits 766 # Number of TLB hits
-system.l1_tlb1.global_TLB_misses 3 # Number of TLB misses
-system.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate
-system.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level
-system.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table
-system.l1_tlb1.unique_pages 3 # Number of unique pages touched
-system.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs
-system.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs
-system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks
-system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses
-system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses
-system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue
-system.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs
-system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts
-system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks
-system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses
-system.l2_tlb.local_TLB_hits 3 # Number of TLB hits
-system.l2_tlb.local_TLB_misses 5 # Number of TLB misses
-system.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate
-system.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses
-system.l2_tlb.global_TLB_hits 3 # Number of TLB hits
-system.l2_tlb.global_TLB_misses 12 # Number of TLB misses
-system.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate
-system.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level
-system.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table
-system.l2_tlb.unique_pages 5 # Number of unique pages touched
-system.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs
-system.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs
-system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks
-system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses
-system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses
-system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue
-system.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs
-system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts
-system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks
-system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses
-system.l3_tlb.local_TLB_hits 0 # Number of TLB hits
-system.l3_tlb.local_TLB_misses 5 # Number of TLB misses
-system.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate
-system.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses
-system.l3_tlb.global_TLB_hits 0 # Number of TLB hits
-system.l3_tlb.global_TLB_misses 12 # Number of TLB misses
-system.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate
-system.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level
-system.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table
-system.l3_tlb.unique_pages 5 # Number of unique pages touched
-system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs
-system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs
-system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.piobus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.piobus.trans_dist::WriteReq 94 # Transaction distribution
-system.piobus.trans_dist::WriteResp 94 # Transaction distribution
-system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.reqLayer0.occupancy 188000 # Layer occupancy (ticks)
-system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks)
-system.piobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.ruby.network.ext_links0.int_node.port_buffers00.avg_buf_msgs 0.001160 # Average number of messages in buffer
-system.ruby.network.ext_links0.int_node.port_buffers00.avg_stall_time 16771.557856 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links0.int_node.port_buffers02.avg_buf_msgs 0.001160 # Average number of messages in buffer
-system.ruby.network.ext_links0.int_node.port_buffers02.avg_stall_time 121180.062406 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links0.int_node.port_buffers04.avg_buf_msgs 0.001160 # Average number of messages in buffer
-system.ruby.network.ext_links0.int_node.port_buffers04.avg_stall_time 16749.523342 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links0.int_node.port_buffers05.avg_buf_msgs 0.000010 # Average number of messages in buffer
-system.ruby.network.ext_links0.int_node.port_buffers05.avg_stall_time 3493.705161 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links0.int_node.port_buffers07.avg_buf_msgs 0.001150 # Average number of messages in buffer
-system.ruby.network.ext_links0.int_node.port_buffers07.avg_stall_time 30490.654510 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links0.int_node.port_buffers15.avg_buf_msgs 0.001150 # Average number of messages in buffer
-system.ruby.network.ext_links0.int_node.port_buffers15.avg_stall_time 30497.737889 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links0.int_node.port_buffers17.avg_buf_msgs 0.000010 # Average number of messages in buffer
-system.ruby.network.ext_links0.int_node.port_buffers17.avg_stall_time 3490.277719 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
+system.cp_cntrl0.L1D0cache.demand_hits 0
+system.cp_cntrl0.L1D0cache.demand_misses 506
+system.cp_cntrl0.L1D0cache.demand_accesses 506
+system.cp_cntrl0.L1D0cache.num_data_array_reads 16155
+system.cp_cntrl0.L1D0cache.num_data_array_writes 11985
+system.cp_cntrl0.L1D0cache.num_tag_array_reads 27132
+system.cp_cntrl0.L1D0cache.num_tag_array_writes 1584
+system.cp_cntrl0.L1D1cache.demand_hits 0
+system.cp_cntrl0.L1D1cache.demand_misses 0
+system.cp_cntrl0.L1D1cache.demand_accesses 0
+system.cp_cntrl0.L1Icache.demand_hits 0
+system.cp_cntrl0.L1Icache.demand_misses 1088
+system.cp_cntrl0.L1Icache.demand_accesses 1088
+system.cp_cntrl0.L1Icache.num_data_array_reads 86007
+system.cp_cntrl0.L1Icache.num_data_array_writes 54
+system.cp_cntrl0.L1Icache.num_tag_array_reads 87684
+system.cp_cntrl0.L1Icache.num_tag_array_writes 54
+system.cp_cntrl0.L2cache.demand_hits 0
+system.cp_cntrl0.L2cache.demand_misses 1535
+system.cp_cntrl0.L2cache.demand_accesses 1535
+system.cp_cntrl0.L2cache.num_data_array_reads 120
+system.cp_cntrl0.L2cache.num_data_array_writes 11982
+system.cp_cntrl0.L2cache.num_tag_array_reads 12057
+system.cp_cntrl0.L2cache.num_tag_array_writes 1649
+system.cp_cntrl0.mandatoryQueue.avg_buf_msgs 0.427713
+system.cp_cntrl0.mandatoryQueue.avg_stall_time 1999.994007
+system.cp_cntrl0.probeToCore.avg_buf_msgs 0.000010
+system.cp_cntrl0.probeToCore.avg_stall_time 3665.454806
+system.cp_cntrl0.requestFromCore.avg_buf_msgs 0.034499
+system.cp_cntrl0.requestFromCore.avg_stall_time 14999.617925
+system.cp_cntrl0.responseFromCore.avg_buf_msgs 0.000315
+system.cp_cntrl0.responseFromCore.avg_stall_time 1717.844815
+system.cp_cntrl0.responseToCore.avg_buf_msgs 0.001150
+system.cp_cntrl0.responseToCore.avg_stall_time 31990.122976
+system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500
+system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 667407500
+system.cp_cntrl0.triggerQueue.avg_buf_msgs 0.001591
+system.cp_cntrl0.triggerQueue.avg_stall_time 15959.959998
+system.cp_cntrl0.unblockFromCore.avg_buf_msgs 0.034499
+system.cp_cntrl0.unblockFromCore.avg_stall_time 14995.033020
+system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500
+system.cpu0.clk_domain.clock 500
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 667407500
+system.cpu0.apic_clk_domain.clock 8000
+system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 667407500
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 667407500
+system.cpu0.workload.numSyscalls 21
+system.cpu0.numPwrStateTransitions 2
+system.cpu0.pwrStateClkGateDist::samples 1
+system.cpu0.pwrStateClkGateDist::mean 2095501
+system.cpu0.pwrStateClkGateDist::1000-5e+10 1 100.00% 100.00%
+system.cpu0.pwrStateClkGateDist::min_value 2095501
+system.cpu0.pwrStateClkGateDist::max_value 2095501
+system.cpu0.pwrStateClkGateDist::total 1
+system.cpu0.pwrStateResidencyTicks::ON 665311999
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2095501
+system.cpu0.numCycles 1334815
+system.cpu0.numWorkItemsStarted 0
+system.cpu0.numWorkItemsCompleted 0
+system.cpu0.committedInsts 66963
+system.cpu0.committedOps 137705
+system.cpu0.num_int_alu_accesses 136380
+system.cpu0.num_fp_alu_accesses 1279
+system.cpu0.num_func_calls 3196
+system.cpu0.num_conditional_control_insts 12151
+system.cpu0.num_int_insts 136380
+system.cpu0.num_fp_insts 1279
+system.cpu0.num_int_register_reads 257490
+system.cpu0.num_int_register_writes 110039
+system.cpu0.num_fp_register_reads 1981
+system.cpu0.num_fp_register_writes 981
+system.cpu0.num_cc_register_reads 78262
+system.cpu0.num_cc_register_writes 42183
+system.cpu0.num_mem_refs 27198
+system.cpu0.num_load_insts 16684
+system.cpu0.num_store_insts 10514
+system.cpu0.num_idle_cycles 4191.003994
+system.cpu0.num_busy_cycles 1330623.996006
+system.cpu0.not_idle_fraction 0.996860
+system.cpu0.idle_fraction 0.003140
+system.cpu0.Branches 16199
+system.cpu0.op_class::No_OpClass 615 0.45% 0.45%
+system.cpu0.op_class::IntAlu 108791 79.00% 79.45%
+system.cpu0.op_class::IntMult 13 0.01% 79.46%
+system.cpu0.op_class::IntDiv 138 0.10% 79.56%
+system.cpu0.op_class::FloatAdd 950 0.69% 80.25%
+system.cpu0.op_class::FloatCmp 0 0.00% 80.25%
+system.cpu0.op_class::FloatCvt 0 0.00% 80.25%
+system.cpu0.op_class::FloatMult 0 0.00% 80.25%
+system.cpu0.op_class::FloatMultAcc 0 0.00% 80.25%
+system.cpu0.op_class::FloatDiv 0 0.00% 80.25%
+system.cpu0.op_class::FloatMisc 0 0.00% 80.25%
+system.cpu0.op_class::FloatSqrt 0 0.00% 80.25%
+system.cpu0.op_class::SimdAdd 0 0.00% 80.25%
+system.cpu0.op_class::SimdAddAcc 0 0.00% 80.25%
+system.cpu0.op_class::SimdAlu 0 0.00% 80.25%
+system.cpu0.op_class::SimdCmp 0 0.00% 80.25%
+system.cpu0.op_class::SimdCvt 0 0.00% 80.25%
+system.cpu0.op_class::SimdMisc 0 0.00% 80.25%
+system.cpu0.op_class::SimdMult 0 0.00% 80.25%
+system.cpu0.op_class::SimdMultAcc 0 0.00% 80.25%
+system.cpu0.op_class::SimdShift 0 0.00% 80.25%
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 80.25%
+system.cpu0.op_class::SimdSqrt 0 0.00% 80.25%
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 80.25%
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 80.25%
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 80.25%
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 80.25%
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 80.25%
+system.cpu0.op_class::SimdFloatMisc 0 0.00% 80.25%
+system.cpu0.op_class::SimdFloatMult 0 0.00% 80.25%
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 80.25%
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25%
+system.cpu0.op_class::MemRead 16382 11.90% 92.15%
+system.cpu0.op_class::MemWrite 10514 7.64% 99.78%
+system.cpu0.op_class::FloatMemRead 302 0.22% 100.00%
+system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00%
+system.cpu0.op_class::IprAccess 0 0.00% 100.00%
+system.cpu0.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu0.op_class::total 137705
+system.cpu1.clk_domain.voltage_domain.voltage 1
+system.cpu1.clk_domain.clock 1000
+system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 667407500
+system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 309
+system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39
+system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872
+system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880
+system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79%
+system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00%
+system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00%
+system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value 2
+system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total 39
+system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples 39
+system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean 0.589744
+system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::stdev 0.498310
+system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00%
+system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00%
+system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::max_value 1
+system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::total 39
+system.cpu1.CUs0.wavefronts01.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts01.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts01.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts02.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts02.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts02.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts03.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts03.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts03.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts04.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts04.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts05.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts05.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts05.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts06.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts06.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts06.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts07.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts07.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 284
+system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34
+system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941
+system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493
+system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59%
+system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00%
+system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00%
+system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value 2
+system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total 34
+system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples 34
+system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean 0.617647
+system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev 0.493270
+system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00%
+system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00%
+system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value 1
+system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total 34
+system.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts10.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts11.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts13.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts14.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts15.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 279
+system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34
+system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941
+system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493
+system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59%
+system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00%
+system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00%
+system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value 2
+system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total 34
+system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples 34
+system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean 0.617647
+system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev 0.493270
+system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00%
+system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00%
+system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value 1
+system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total 34
+system.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts21.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts22.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts23.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 274
+system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34
+system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941
+system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493
+system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59%
+system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00%
+system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00%
+system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value 2
+system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total 34
+system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples 34
+system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean 0.617647
+system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev 0.493270
+system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00%
+system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00%
+system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value 1
+system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total 34
+system.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4 0
+system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total 0
+system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples 0
+system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean nan
+system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0
+system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 667407500
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 35
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 11.257143
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 5.595917
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 4 11.43% 11.43%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 4 11.43% 22.86%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.86% 25.71%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 25.71%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 0 0.00% 25.71%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 25.71%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 0 0.00% 25.71%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 25.71%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 4 11.43% 37.14%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 4 11.43% 48.57%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 48.57%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 48.57%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 1 2.86% 51.43%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 51.43%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 17 48.57% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00%
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 16
+system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 35
+system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 2741
+system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 99
+system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30
+system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29
+system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29
+system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29
+system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18
+system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6
+system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 625
+system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 340
+system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 338
+system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 335
+system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 404
+system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 22
+system.cpu1.CUs0.ExecStage.spc::samples 2840
+system.cpu1.CUs0.ExecStage.spc::mean 0.049648
+system.cpu1.CUs0.ExecStage.spc::stdev 0.277106
+system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.ExecStage.spc::0 2741 96.51% 96.51%
+system.cpu1.CUs0.ExecStage.spc::1 57 2.01% 98.52%
+system.cpu1.CUs0.ExecStage.spc::2 42 1.48% 100.00%
+system.cpu1.CUs0.ExecStage.spc::3 0 0.00% 100.00%
+system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00%
+system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00%
+system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00%
+system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00%
+system.cpu1.CUs0.ExecStage.spc::min_value 0
+system.cpu1.CUs0.ExecStage.spc::max_value 2
+system.cpu1.CUs0.ExecStage.spc::total 2840
+system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 90
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 90
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 29.322222
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 145.995831
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 76 84.44% 84.44%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.78% 92.22%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 92.22%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 92.22%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 0 0.00% 92.22%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.11% 93.33%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 93.33%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 93.33%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 93.33%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 93.33%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 93.33%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 93.33%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 93.33%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 93.33%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 93.33%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 93.33%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 6 6.67% 100.00%
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1291
+system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 90
+system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0
+system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0
+system.cpu1.CUs0.valu_insts 68
+system.cpu1.CUs0.valu_insts_per_wf 17
+system.cpu1.CUs0.salu_insts 0
+system.cpu1.CUs0.salu_insts_per_wf 0
+system.cpu1.CUs0.inst_cycles_valu 68
+system.cpu1.CUs0.inst_cycles_salu 0
+system.cpu1.CUs0.thread_cycles_valu 3076
+system.cpu1.CUs0.valu_utilization 70.680147
+system.cpu1.CUs0.lds_no_flat_insts 6
+system.cpu1.CUs0.lds_no_flat_insts_per_wf 1.500000
+system.cpu1.CUs0.flat_vmem_insts 0
+system.cpu1.CUs0.flat_vmem_insts_per_wf 0
+system.cpu1.CUs0.flat_lds_insts 0
+system.cpu1.CUs0.flat_lds_insts_per_wf 0
+system.cpu1.CUs0.vector_mem_writes 8
+system.cpu1.CUs0.vector_mem_writes_per_wf 2
+system.cpu1.CUs0.vector_mem_reads 29
+system.cpu1.CUs0.vector_mem_reads_per_wf 7.250000
+system.cpu1.CUs0.scalar_mem_writes 0
+system.cpu1.CUs0.scalar_mem_writes_per_wf 0
+system.cpu1.CUs0.scalar_mem_reads 0
+system.cpu1.CUs0.scalar_mem_reads_per_wf 0
+system.cpu1.CUs0.tlb_requests 769
+system.cpu1.CUs0.tlb_cycles -454892896000
+system.cpu1.CUs0.avg_translation_latency -591538226.267880
+system.cpu1.CUs0.TLB_hits_distribution::page_table 769
+system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0
+system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0
+system.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0
+system.cpu1.CUs0.lds_bank_access_cnt 54
+system.cpu1.CUs0.lds_bank_conflicts::samples 6
+system.cpu1.CUs0.lds_bank_conflicts::mean 8
+system.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773
+system.cpu1.CUs0.lds_bank_conflicts::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.lds_bank_conflicts::0-1 2 33.33% 33.33%
+system.cpu1.CUs0.lds_bank_conflicts::2-3 0 0.00% 33.33%
+system.cpu1.CUs0.lds_bank_conflicts::4-5 0 0.00% 33.33%
+system.cpu1.CUs0.lds_bank_conflicts::6-7 0 0.00% 33.33%
+system.cpu1.CUs0.lds_bank_conflicts::8-9 0 0.00% 33.33%
+system.cpu1.CUs0.lds_bank_conflicts::10-11 0 0.00% 33.33%
+system.cpu1.CUs0.lds_bank_conflicts::12-13 4 66.67% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::14-15 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::16-17 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::18-19 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::20-21 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::22-23 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::24-25 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::26-27 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::28-29 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::30-31 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::32-33 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::34-35 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::36-37 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::38-39 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::40-41 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::42-43 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::44-45 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::46-47 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::48-49 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::50-51 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::52-53 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::54-55 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::56-57 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::58-59 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::60-61 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::62-63 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::64 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::overflows 0 0.00% 100.00%
+system.cpu1.CUs0.lds_bank_conflicts::min_value 0
+system.cpu1.CUs0.lds_bank_conflicts::max_value 12
+system.cpu1.CUs0.lds_bank_conflicts::total 6
+system.cpu1.CUs0.page_divergence_dist::samples 17
+system.cpu1.CUs0.page_divergence_dist::mean 1
+system.cpu1.CUs0.page_divergence_dist::stdev 0
+system.cpu1.CUs0.page_divergence_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.page_divergence_dist::1-4 17 100.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::5-8 0 0.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::9-12 0 0.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::13-16 0 0.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::17-20 0 0.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::21-24 0 0.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::25-28 0 0.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::29-32 0 0.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::33-36 0 0.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::37-40 0 0.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::41-44 0 0.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::45-48 0 0.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::49-52 0 0.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::53-56 0 0.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::57-60 0 0.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::61-64 0 0.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs0.page_divergence_dist::min_value 1
+system.cpu1.CUs0.page_divergence_dist::max_value 1
+system.cpu1.CUs0.page_divergence_dist::total 17
+system.cpu1.CUs0.global_mem_instr_cnt 17
+system.cpu1.CUs0.local_mem_instr_cnt 6
+system.cpu1.CUs0.wg_blocked_due_lds_alloc 0
+system.cpu1.CUs0.num_instr_executed 141
+system.cpu1.CUs0.inst_exec_rate::samples 141
+system.cpu1.CUs0.inst_exec_rate::mean 71.028369
+system.cpu1.CUs0.inst_exec_rate::stdev 225.061514
+system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.inst_exec_rate::0-1 0 0.00% 0.00%
+system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 8.51%
+system.cpu1.CUs0.inst_exec_rate::4-5 61 43.26% 51.77%
+system.cpu1.CUs0.inst_exec_rate::6-7 32 22.70% 74.47%
+system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 76.60%
+system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 78.72%
+system.cpu1.CUs0.inst_exec_rate::overflows 30 21.28% 100.00%
+system.cpu1.CUs0.inst_exec_rate::min_value 2
+system.cpu1.CUs0.inst_exec_rate::max_value 1297
+system.cpu1.CUs0.inst_exec_rate::total 141
+system.cpu1.CUs0.num_vec_ops_executed 6769
+system.cpu1.CUs0.num_total_cycles 2840
+system.cpu1.CUs0.vpc 2.383451
+system.cpu1.CUs0.ipc 0.049648
+system.cpu1.CUs0.warp_execution_dist::samples 141
+system.cpu1.CUs0.warp_execution_dist::mean 48.007092
+system.cpu1.CUs0.warp_execution_dist::stdev 23.719942
+system.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55%
+system.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55%
+system.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55%
+system.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08%
+system.cpu1.CUs0.warp_execution_dist::17-20 0 0.00% 29.08%
+system.cpu1.CUs0.warp_execution_dist::21-24 0 0.00% 29.08%
+system.cpu1.CUs0.warp_execution_dist::25-28 0 0.00% 29.08%
+system.cpu1.CUs0.warp_execution_dist::29-32 0 0.00% 29.08%
+system.cpu1.CUs0.warp_execution_dist::33-36 0 0.00% 29.08%
+system.cpu1.CUs0.warp_execution_dist::37-40 0 0.00% 29.08%
+system.cpu1.CUs0.warp_execution_dist::41-44 0 0.00% 29.08%
+system.cpu1.CUs0.warp_execution_dist::45-48 0 0.00% 29.08%
+system.cpu1.CUs0.warp_execution_dist::49-52 8 5.67% 34.75%
+system.cpu1.CUs0.warp_execution_dist::53-56 0 0.00% 34.75%
+system.cpu1.CUs0.warp_execution_dist::57-60 0 0.00% 34.75%
+system.cpu1.CUs0.warp_execution_dist::61-64 92 65.25% 100.00%
+system.cpu1.CUs0.warp_execution_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs0.warp_execution_dist::min_value 1
+system.cpu1.CUs0.warp_execution_dist::max_value 64
+system.cpu1.CUs0.warp_execution_dist::total 141
+system.cpu1.CUs0.gmem_lanes_execution_dist::samples 18
+system.cpu1.CUs0.gmem_lanes_execution_dist::mean 37.833333
+system.cpu1.CUs0.gmem_lanes_execution_dist::stdev 27.064737
+system.cpu1.CUs0.gmem_lanes_execution_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.gmem_lanes_execution_dist::1-4 1 5.56% 5.56%
+system.cpu1.CUs0.gmem_lanes_execution_dist::5-8 0 0.00% 5.56%
+system.cpu1.CUs0.gmem_lanes_execution_dist::9-12 0 0.00% 5.56%
+system.cpu1.CUs0.gmem_lanes_execution_dist::13-16 8 44.44% 50.00%
+system.cpu1.CUs0.gmem_lanes_execution_dist::17-20 0 0.00% 50.00%
+system.cpu1.CUs0.gmem_lanes_execution_dist::21-24 0 0.00% 50.00%
+system.cpu1.CUs0.gmem_lanes_execution_dist::25-28 0 0.00% 50.00%
+system.cpu1.CUs0.gmem_lanes_execution_dist::29-32 0 0.00% 50.00%
+system.cpu1.CUs0.gmem_lanes_execution_dist::33-36 0 0.00% 50.00%
+system.cpu1.CUs0.gmem_lanes_execution_dist::37-40 0 0.00% 50.00%
+system.cpu1.CUs0.gmem_lanes_execution_dist::41-44 0 0.00% 50.00%
+system.cpu1.CUs0.gmem_lanes_execution_dist::45-48 0 0.00% 50.00%
+system.cpu1.CUs0.gmem_lanes_execution_dist::49-52 0 0.00% 50.00%
+system.cpu1.CUs0.gmem_lanes_execution_dist::53-56 0 0.00% 50.00%
+system.cpu1.CUs0.gmem_lanes_execution_dist::57-60 0 0.00% 50.00%
+system.cpu1.CUs0.gmem_lanes_execution_dist::61-64 9 50.00% 100.00%
+system.cpu1.CUs0.gmem_lanes_execution_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs0.gmem_lanes_execution_dist::min_value 1
+system.cpu1.CUs0.gmem_lanes_execution_dist::max_value 64
+system.cpu1.CUs0.gmem_lanes_execution_dist::total 18
+system.cpu1.CUs0.lmem_lanes_execution_dist::samples 6
+system.cpu1.CUs0.lmem_lanes_execution_dist::mean 19.500000
+system.cpu1.CUs0.lmem_lanes_execution_dist::stdev 22.322634
+system.cpu1.CUs0.lmem_lanes_execution_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs0.lmem_lanes_execution_dist::1-4 1 16.67% 16.67%
+system.cpu1.CUs0.lmem_lanes_execution_dist::5-8 0 0.00% 16.67%
+system.cpu1.CUs0.lmem_lanes_execution_dist::9-12 0 0.00% 16.67%
+system.cpu1.CUs0.lmem_lanes_execution_dist::13-16 4 66.67% 83.33%
+system.cpu1.CUs0.lmem_lanes_execution_dist::17-20 0 0.00% 83.33%
+system.cpu1.CUs0.lmem_lanes_execution_dist::21-24 0 0.00% 83.33%
+system.cpu1.CUs0.lmem_lanes_execution_dist::25-28 0 0.00% 83.33%
+system.cpu1.CUs0.lmem_lanes_execution_dist::29-32 0 0.00% 83.33%
+system.cpu1.CUs0.lmem_lanes_execution_dist::33-36 0 0.00% 83.33%
+system.cpu1.CUs0.lmem_lanes_execution_dist::37-40 0 0.00% 83.33%
+system.cpu1.CUs0.lmem_lanes_execution_dist::41-44 0 0.00% 83.33%
+system.cpu1.CUs0.lmem_lanes_execution_dist::45-48 0 0.00% 83.33%
+system.cpu1.CUs0.lmem_lanes_execution_dist::49-52 0 0.00% 83.33%
+system.cpu1.CUs0.lmem_lanes_execution_dist::53-56 0 0.00% 83.33%
+system.cpu1.CUs0.lmem_lanes_execution_dist::57-60 0 0.00% 83.33%
+system.cpu1.CUs0.lmem_lanes_execution_dist::61-64 1 16.67% 100.00%
+system.cpu1.CUs0.lmem_lanes_execution_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1
+system.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64
+system.cpu1.CUs0.lmem_lanes_execution_dist::total 6
+system.cpu1.CUs0.num_alu_insts_executed 118
+system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0
+system.cpu1.CUs0.num_CAS_ops 0
+system.cpu1.CUs0.num_failed_CAS_ops 0
+system.cpu1.CUs0.num_completed_wfs 4
+system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 667407500
+system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 406
+system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39
+system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872
+system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880
+system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79%
+system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00%
+system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00%
+system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value 2
+system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total 39
+system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples 39
+system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean 0.589744
+system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev 0.498310
+system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00%
+system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00%
+system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value 1
+system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total 39
+system.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts02.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts03.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts03.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts03.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts04.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts04.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts04.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts05.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts06.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts06.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts06.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts07.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts07.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts07.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 381
+system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34
+system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941
+system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493
+system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59%
+system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00%
+system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00%
+system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value 2
+system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total 34
+system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples 34
+system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean 0.617647
+system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev 0.493270
+system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00%
+system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00%
+system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value 1
+system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total 34
+system.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts11.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts12.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts13.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts14.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts15.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 372
+system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34
+system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941
+system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493
+system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59%
+system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00%
+system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00%
+system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value 2
+system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total 34
+system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples 34
+system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean 0.617647
+system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev 0.493270
+system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00%
+system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00%
+system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value 1
+system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total 34
+system.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts19.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts20.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts21.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts22.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts23.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 364
+system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34
+system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941
+system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493
+system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59%
+system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00%
+system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00%
+system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value 2
+system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total 34
+system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples 34
+system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean 0.617647
+system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev 0.493270
+system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00%
+system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00%
+system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value 1
+system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total 34
+system.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts27.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts27.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail 0
+system.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies 0
+system.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies 0
+system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4 0
+system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total 0
+system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples 0
+system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean nan
+system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan
+system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0
+system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0
+system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0
+system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0
+system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0
+system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0
+system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0
+system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 667407500
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 35
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 11.257143
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 5.595917
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 4 11.43% 11.43%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 4 11.43% 22.86%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.86% 25.71%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 25.71%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 0 0.00% 25.71%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 25.71%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 0 0.00% 25.71%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 25.71%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 4 11.43% 37.14%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 4 11.43% 48.57%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 48.57%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 48.57%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 1 2.86% 51.43%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 51.43%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 17 48.57% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00%
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 16
+system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 35
+system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 2740
+system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 100
+system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30
+system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29
+system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29
+system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29
+system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18
+system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6
+system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 795
+system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 437
+system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 431
+system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 422
+system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 408
+system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 22
+system.cpu1.CUs1.ExecStage.spc::samples 2840
+system.cpu1.CUs1.ExecStage.spc::mean 0.049648
+system.cpu1.CUs1.ExecStage.spc::stdev 0.275831
+system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.ExecStage.spc::0 2740 96.48% 96.48%
+system.cpu1.CUs1.ExecStage.spc::1 59 2.08% 98.56%
+system.cpu1.CUs1.ExecStage.spc::2 41 1.44% 100.00%
+system.cpu1.CUs1.ExecStage.spc::3 0 0.00% 100.00%
+system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00%
+system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00%
+system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00%
+system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00%
+system.cpu1.CUs1.ExecStage.spc::min_value 0
+system.cpu1.CUs1.ExecStage.spc::max_value 2
+system.cpu1.CUs1.ExecStage.spc::total 2840
+system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 91
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 91
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 30.010989
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 148.108031
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 76 83.52% 83.52%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.79% 92.31%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 92.31%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 92.31%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 0 0.00% 92.31%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.10% 93.41%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 93.41%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 93.41%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 93.41%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 93.41%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 93.41%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 93.41%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 93.41%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 93.41%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 93.41%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 93.41%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 6 6.59% 100.00%
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1299
+system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 91
+system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0
+system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0
+system.cpu1.CUs1.valu_insts 68
+system.cpu1.CUs1.valu_insts_per_wf 17
+system.cpu1.CUs1.salu_insts 0
+system.cpu1.CUs1.salu_insts_per_wf 0
+system.cpu1.CUs1.inst_cycles_valu 68
+system.cpu1.CUs1.inst_cycles_salu 0
+system.cpu1.CUs1.thread_cycles_valu 3071
+system.cpu1.CUs1.valu_utilization 70.565257
+system.cpu1.CUs1.lds_no_flat_insts 6
+system.cpu1.CUs1.lds_no_flat_insts_per_wf 1.500000
+system.cpu1.CUs1.flat_vmem_insts 0
+system.cpu1.CUs1.flat_vmem_insts_per_wf 0
+system.cpu1.CUs1.flat_lds_insts 0
+system.cpu1.CUs1.flat_lds_insts_per_wf 0
+system.cpu1.CUs1.vector_mem_writes 8
+system.cpu1.CUs1.vector_mem_writes_per_wf 2
+system.cpu1.CUs1.vector_mem_reads 29
+system.cpu1.CUs1.vector_mem_reads_per_wf 7.250000
+system.cpu1.CUs1.scalar_mem_writes 0
+system.cpu1.CUs1.scalar_mem_writes_per_wf 0
+system.cpu1.CUs1.scalar_mem_reads 0
+system.cpu1.CUs1.scalar_mem_reads_per_wf 0
+system.cpu1.CUs1.tlb_requests 769
+system.cpu1.CUs1.tlb_cycles -454919630000
+system.cpu1.CUs1.avg_translation_latency -591572990.897269
+system.cpu1.CUs1.TLB_hits_distribution::page_table 769
+system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0
+system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0
+system.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0
+system.cpu1.CUs1.lds_bank_access_cnt 53
+system.cpu1.CUs1.lds_bank_conflicts::samples 6
+system.cpu1.CUs1.lds_bank_conflicts::mean 7.833333
+system.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022
+system.cpu1.CUs1.lds_bank_conflicts::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.lds_bank_conflicts::0-1 2 33.33% 33.33%
+system.cpu1.CUs1.lds_bank_conflicts::2-3 0 0.00% 33.33%
+system.cpu1.CUs1.lds_bank_conflicts::4-5 0 0.00% 33.33%
+system.cpu1.CUs1.lds_bank_conflicts::6-7 0 0.00% 33.33%
+system.cpu1.CUs1.lds_bank_conflicts::8-9 0 0.00% 33.33%
+system.cpu1.CUs1.lds_bank_conflicts::10-11 1 16.67% 50.00%
+system.cpu1.CUs1.lds_bank_conflicts::12-13 3 50.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::14-15 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::16-17 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::18-19 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::20-21 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::22-23 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::24-25 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::26-27 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::28-29 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::30-31 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::32-33 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::34-35 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::36-37 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::38-39 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::40-41 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::42-43 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::44-45 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::46-47 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::48-49 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::50-51 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::52-53 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::54-55 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::56-57 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::58-59 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::60-61 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::62-63 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::64 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::overflows 0 0.00% 100.00%
+system.cpu1.CUs1.lds_bank_conflicts::min_value 0
+system.cpu1.CUs1.lds_bank_conflicts::max_value 12
+system.cpu1.CUs1.lds_bank_conflicts::total 6
+system.cpu1.CUs1.page_divergence_dist::samples 17
+system.cpu1.CUs1.page_divergence_dist::mean 1
+system.cpu1.CUs1.page_divergence_dist::stdev 0
+system.cpu1.CUs1.page_divergence_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.page_divergence_dist::1-4 17 100.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::5-8 0 0.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::9-12 0 0.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::13-16 0 0.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::17-20 0 0.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::21-24 0 0.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::25-28 0 0.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::29-32 0 0.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::33-36 0 0.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::37-40 0 0.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::41-44 0 0.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::45-48 0 0.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::49-52 0 0.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::53-56 0 0.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::57-60 0 0.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::61-64 0 0.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs1.page_divergence_dist::min_value 1
+system.cpu1.CUs1.page_divergence_dist::max_value 1
+system.cpu1.CUs1.page_divergence_dist::total 17
+system.cpu1.CUs1.global_mem_instr_cnt 17
+system.cpu1.CUs1.local_mem_instr_cnt 6
+system.cpu1.CUs1.wg_blocked_due_lds_alloc 0
+system.cpu1.CUs1.num_instr_executed 141
+system.cpu1.CUs1.inst_exec_rate::samples 141
+system.cpu1.CUs1.inst_exec_rate::mean 72.113475
+system.cpu1.CUs1.inst_exec_rate::stdev 228.065470
+system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.inst_exec_rate::0-1 0 0.00% 0.00%
+system.cpu1.CUs1.inst_exec_rate::2-3 13 9.22% 9.22%
+system.cpu1.CUs1.inst_exec_rate::4-5 60 42.55% 51.77%
+system.cpu1.CUs1.inst_exec_rate::6-7 34 24.11% 75.89%
+system.cpu1.CUs1.inst_exec_rate::8-9 3 2.13% 78.01%
+system.cpu1.CUs1.inst_exec_rate::10 1 0.71% 78.72%
+system.cpu1.CUs1.inst_exec_rate::overflows 30 21.28% 100.00%
+system.cpu1.CUs1.inst_exec_rate::min_value 2
+system.cpu1.CUs1.inst_exec_rate::max_value 1305
+system.cpu1.CUs1.inst_exec_rate::total 141
+system.cpu1.CUs1.num_vec_ops_executed 6762
+system.cpu1.CUs1.num_total_cycles 2840
+system.cpu1.CUs1.vpc 2.380986
+system.cpu1.CUs1.ipc 0.049648
+system.cpu1.CUs1.warp_execution_dist::samples 141
+system.cpu1.CUs1.warp_execution_dist::mean 47.957447
+system.cpu1.CUs1.warp_execution_dist::stdev 23.818022
+system.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55%
+system.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55%
+system.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93%
+system.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08%
+system.cpu1.CUs1.warp_execution_dist::17-20 0 0.00% 29.08%
+system.cpu1.CUs1.warp_execution_dist::21-24 0 0.00% 29.08%
+system.cpu1.CUs1.warp_execution_dist::25-28 0 0.00% 29.08%
+system.cpu1.CUs1.warp_execution_dist::29-32 0 0.00% 29.08%
+system.cpu1.CUs1.warp_execution_dist::33-36 0 0.00% 29.08%
+system.cpu1.CUs1.warp_execution_dist::37-40 0 0.00% 29.08%
+system.cpu1.CUs1.warp_execution_dist::41-44 0 0.00% 29.08%
+system.cpu1.CUs1.warp_execution_dist::45-48 0 0.00% 29.08%
+system.cpu1.CUs1.warp_execution_dist::49-52 8 5.67% 34.75%
+system.cpu1.CUs1.warp_execution_dist::53-56 0 0.00% 34.75%
+system.cpu1.CUs1.warp_execution_dist::57-60 0 0.00% 34.75%
+system.cpu1.CUs1.warp_execution_dist::61-64 92 65.25% 100.00%
+system.cpu1.CUs1.warp_execution_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs1.warp_execution_dist::min_value 1
+system.cpu1.CUs1.warp_execution_dist::max_value 64
+system.cpu1.CUs1.warp_execution_dist::total 141
+system.cpu1.CUs1.gmem_lanes_execution_dist::samples 18
+system.cpu1.CUs1.gmem_lanes_execution_dist::mean 37.722222
+system.cpu1.CUs1.gmem_lanes_execution_dist::stdev 27.174394
+system.cpu1.CUs1.gmem_lanes_execution_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.gmem_lanes_execution_dist::1-4 1 5.56% 5.56%
+system.cpu1.CUs1.gmem_lanes_execution_dist::5-8 0 0.00% 5.56%
+system.cpu1.CUs1.gmem_lanes_execution_dist::9-12 2 11.11% 16.67%
+system.cpu1.CUs1.gmem_lanes_execution_dist::13-16 6 33.33% 50.00%
+system.cpu1.CUs1.gmem_lanes_execution_dist::17-20 0 0.00% 50.00%
+system.cpu1.CUs1.gmem_lanes_execution_dist::21-24 0 0.00% 50.00%
+system.cpu1.CUs1.gmem_lanes_execution_dist::25-28 0 0.00% 50.00%
+system.cpu1.CUs1.gmem_lanes_execution_dist::29-32 0 0.00% 50.00%
+system.cpu1.CUs1.gmem_lanes_execution_dist::33-36 0 0.00% 50.00%
+system.cpu1.CUs1.gmem_lanes_execution_dist::37-40 0 0.00% 50.00%
+system.cpu1.CUs1.gmem_lanes_execution_dist::41-44 0 0.00% 50.00%
+system.cpu1.CUs1.gmem_lanes_execution_dist::45-48 0 0.00% 50.00%
+system.cpu1.CUs1.gmem_lanes_execution_dist::49-52 0 0.00% 50.00%
+system.cpu1.CUs1.gmem_lanes_execution_dist::53-56 0 0.00% 50.00%
+system.cpu1.CUs1.gmem_lanes_execution_dist::57-60 0 0.00% 50.00%
+system.cpu1.CUs1.gmem_lanes_execution_dist::61-64 9 50.00% 100.00%
+system.cpu1.CUs1.gmem_lanes_execution_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs1.gmem_lanes_execution_dist::min_value 1
+system.cpu1.CUs1.gmem_lanes_execution_dist::max_value 64
+system.cpu1.CUs1.gmem_lanes_execution_dist::total 18
+system.cpu1.CUs1.lmem_lanes_execution_dist::samples 6
+system.cpu1.CUs1.lmem_lanes_execution_dist::mean 19.333333
+system.cpu1.CUs1.lmem_lanes_execution_dist::stdev 22.384518
+system.cpu1.CUs1.lmem_lanes_execution_dist::underflows 0 0.00% 0.00%
+system.cpu1.CUs1.lmem_lanes_execution_dist::1-4 1 16.67% 16.67%
+system.cpu1.CUs1.lmem_lanes_execution_dist::5-8 0 0.00% 16.67%
+system.cpu1.CUs1.lmem_lanes_execution_dist::9-12 1 16.67% 33.33%
+system.cpu1.CUs1.lmem_lanes_execution_dist::13-16 3 50.00% 83.33%
+system.cpu1.CUs1.lmem_lanes_execution_dist::17-20 0 0.00% 83.33%
+system.cpu1.CUs1.lmem_lanes_execution_dist::21-24 0 0.00% 83.33%
+system.cpu1.CUs1.lmem_lanes_execution_dist::25-28 0 0.00% 83.33%
+system.cpu1.CUs1.lmem_lanes_execution_dist::29-32 0 0.00% 83.33%
+system.cpu1.CUs1.lmem_lanes_execution_dist::33-36 0 0.00% 83.33%
+system.cpu1.CUs1.lmem_lanes_execution_dist::37-40 0 0.00% 83.33%
+system.cpu1.CUs1.lmem_lanes_execution_dist::41-44 0 0.00% 83.33%
+system.cpu1.CUs1.lmem_lanes_execution_dist::45-48 0 0.00% 83.33%
+system.cpu1.CUs1.lmem_lanes_execution_dist::49-52 0 0.00% 83.33%
+system.cpu1.CUs1.lmem_lanes_execution_dist::53-56 0 0.00% 83.33%
+system.cpu1.CUs1.lmem_lanes_execution_dist::57-60 0 0.00% 83.33%
+system.cpu1.CUs1.lmem_lanes_execution_dist::61-64 1 16.67% 100.00%
+system.cpu1.CUs1.lmem_lanes_execution_dist::overflows 0 0.00% 100.00%
+system.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1
+system.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64
+system.cpu1.CUs1.lmem_lanes_execution_dist::total 6
+system.cpu1.CUs1.num_alu_insts_executed 118
+system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0
+system.cpu1.CUs1.num_CAS_ops 0
+system.cpu1.CUs1.num_failed_CAS_ops 0
+system.cpu1.CUs1.num_completed_wfs 4
+system.cpu1.pwrStateResidencyTicks::UNDEFINED 667407500
+system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 667407500
+system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 667407500
+system.cpu2.pwrStateResidencyTicks::UNDEFINED 667407500
+system.cpu2.num_kernel_launched 1
+system.dir_cntrl0.L3CacheMemory.demand_hits 0
+system.dir_cntrl0.L3CacheMemory.demand_misses 0
+system.dir_cntrl0.L3CacheMemory.demand_accesses 0
+system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1549
+system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1549
+system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1549
+system.dir_cntrl0.probeToCore.avg_buf_msgs 0.069628
+system.dir_cntrl0.probeToCore.avg_stall_time 29997.797448
+system.dir_cntrl0.requestFromCores.avg_buf_msgs 0.001160
+system.dir_cntrl0.requestFromCores.avg_stall_time 17271.531260
+system.dir_cntrl0.responseFromCores.avg_buf_msgs 0.001160
+system.dir_cntrl0.responseFromCores.avg_stall_time 121679.841776
+system.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.003110
+system.dir_cntrl0.responseFromMemory.avg_stall_time 999.889123
+system.dir_cntrl0.responseToCore.avg_buf_msgs 0.069628
+system.dir_cntrl0.responseToCore.avg_stall_time 29990.830190
+system.dir_cntrl0.triggerQueue.avg_buf_msgs 0.002321
+system.dir_cntrl0.triggerQueue.avg_stall_time 999.739290
+system.dir_cntrl0.unblockFromCores.avg_buf_msgs 0.001160
+system.dir_cntrl0.unblockFromCores.avg_stall_time 17249.343916
+system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500
+system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1
+system.dispatcher_coalescer.clk_domain.clock 1000
+system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500
+system.dispatcher_coalescer.uncoalesced_accesses 0
+system.dispatcher_coalescer.coalesced_accesses 0
+system.dispatcher_coalescer.queuing_cycles 0
+system.dispatcher_coalescer.local_queuing_cycles 0
+system.dispatcher_coalescer.local_latency nan
+system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1
+system.dispatcher_tlb.clk_domain.clock 1000
+system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 667407500
+system.dispatcher_tlb.local_TLB_accesses 0
+system.dispatcher_tlb.local_TLB_hits 0
+system.dispatcher_tlb.local_TLB_misses 0
+system.dispatcher_tlb.local_TLB_miss_rate nan
+system.dispatcher_tlb.global_TLB_accesses 0
+system.dispatcher_tlb.global_TLB_hits 0
+system.dispatcher_tlb.global_TLB_misses 0
+system.dispatcher_tlb.global_TLB_miss_rate nan
+system.dispatcher_tlb.access_cycles 0
+system.dispatcher_tlb.page_table_cycles 0
+system.dispatcher_tlb.unique_pages 0
+system.dispatcher_tlb.local_cycles 0
+system.dispatcher_tlb.local_latency nan
+system.dispatcher_tlb.avg_reuse_distance 0
+system.l1_coalescer0.clk_domain.voltage_domain.voltage 1
+system.l1_coalescer0.clk_domain.clock 1000
+system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 667407500
+system.l1_coalescer0.uncoalesced_accesses 778
+system.l1_coalescer0.coalesced_accesses 0
+system.l1_coalescer0.queuing_cycles 0
+system.l1_coalescer0.local_queuing_cycles 0
+system.l1_coalescer0.local_latency 0
+system.l1_coalescer1.clk_domain.voltage_domain.voltage 1
+system.l1_coalescer1.clk_domain.clock 1000
+system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 667407500
+system.l1_coalescer1.uncoalesced_accesses 769
+system.l1_coalescer1.coalesced_accesses 0
+system.l1_coalescer1.queuing_cycles 0
+system.l1_coalescer1.local_queuing_cycles 0
+system.l1_coalescer1.local_latency 0
+system.l1_tlb0.clk_domain.voltage_domain.voltage 1
+system.l1_tlb0.clk_domain.clock 1000
+system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 667407500
+system.l1_tlb0.local_TLB_accesses 778
+system.l1_tlb0.local_TLB_hits 774
+system.l1_tlb0.local_TLB_misses 4
+system.l1_tlb0.local_TLB_miss_rate 0.514139
+system.l1_tlb0.global_TLB_accesses 778
+system.l1_tlb0.global_TLB_hits 774
+system.l1_tlb0.global_TLB_misses 4
+system.l1_tlb0.global_TLB_miss_rate 0.514139
+system.l1_tlb0.access_cycles 0
+system.l1_tlb0.page_table_cycles 0
+system.l1_tlb0.unique_pages 4
+system.l1_tlb0.local_cycles 0
+system.l1_tlb0.local_latency 0
+system.l1_tlb0.avg_reuse_distance 0
+system.l1_tlb1.clk_domain.voltage_domain.voltage 1
+system.l1_tlb1.clk_domain.clock 1000
+system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 667407500
+system.l1_tlb1.local_TLB_accesses 769
+system.l1_tlb1.local_TLB_hits 766
+system.l1_tlb1.local_TLB_misses 3
+system.l1_tlb1.local_TLB_miss_rate 0.390117
+system.l1_tlb1.global_TLB_accesses 769
+system.l1_tlb1.global_TLB_hits 766
+system.l1_tlb1.global_TLB_misses 3
+system.l1_tlb1.global_TLB_miss_rate 0.390117
+system.l1_tlb1.access_cycles 0
+system.l1_tlb1.page_table_cycles 0
+system.l1_tlb1.unique_pages 3
+system.l1_tlb1.local_cycles 0
+system.l1_tlb1.local_latency 0
+system.l1_tlb1.avg_reuse_distance 0
+system.l2_coalescer.clk_domain.voltage_domain.voltage 1
+system.l2_coalescer.clk_domain.clock 1000
+system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500
+system.l2_coalescer.uncoalesced_accesses 8
+system.l2_coalescer.coalesced_accesses 1
+system.l2_coalescer.queuing_cycles 8000
+system.l2_coalescer.local_queuing_cycles 1000
+system.l2_coalescer.local_latency 125
+system.l2_tlb.clk_domain.voltage_domain.voltage 1
+system.l2_tlb.clk_domain.clock 1000
+system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 667407500
+system.l2_tlb.local_TLB_accesses 8
+system.l2_tlb.local_TLB_hits 3
+system.l2_tlb.local_TLB_misses 5
+system.l2_tlb.local_TLB_miss_rate 62.500000
+system.l2_tlb.global_TLB_accesses 15
+system.l2_tlb.global_TLB_hits 3
+system.l2_tlb.global_TLB_misses 12
+system.l2_tlb.global_TLB_miss_rate 80
+system.l2_tlb.access_cycles 552008
+system.l2_tlb.page_table_cycles 0
+system.l2_tlb.unique_pages 5
+system.l2_tlb.local_cycles 69001
+system.l2_tlb.local_latency 8625.125000
+system.l2_tlb.avg_reuse_distance 0
+system.l3_coalescer.clk_domain.voltage_domain.voltage 1
+system.l3_coalescer.clk_domain.clock 1000
+system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500
+system.l3_coalescer.uncoalesced_accesses 5
+system.l3_coalescer.coalesced_accesses 1
+system.l3_coalescer.queuing_cycles 8000
+system.l3_coalescer.local_queuing_cycles 1000
+system.l3_coalescer.local_latency 200
+system.l3_tlb.clk_domain.voltage_domain.voltage 1
+system.l3_tlb.clk_domain.clock 1000
+system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 667407500
+system.l3_tlb.local_TLB_accesses 5
+system.l3_tlb.local_TLB_hits 0
+system.l3_tlb.local_TLB_misses 5
+system.l3_tlb.local_TLB_miss_rate 100
+system.l3_tlb.global_TLB_accesses 12
+system.l3_tlb.global_TLB_hits 0
+system.l3_tlb.global_TLB_misses 12
+system.l3_tlb.global_TLB_miss_rate 100
+system.l3_tlb.access_cycles 1200000
+system.l3_tlb.page_table_cycles 6000000
+system.l3_tlb.unique_pages 5
+system.l3_tlb.local_cycles 150000
+system.l3_tlb.local_latency 30000
+system.l3_tlb.avg_reuse_distance 0
+system.piobus.pwrStateResidencyTicks::UNDEFINED 667407500
+system.piobus.trans_dist::WriteReq 94
+system.piobus.trans_dist::WriteResp 94
+system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188
+system.piobus.pkt_count::total 188
+system.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748
+system.piobus.pkt_size::total 748
+system.piobus.reqLayer0.occupancy 188000
+system.piobus.reqLayer0.utilization 0.0
+system.piobus.respLayer0.occupancy 94000
+system.piobus.respLayer0.utilization 0.0
+system.ruby.network.ext_links0.int_node.port_buffers00.avg_buf_msgs 0.001160
+system.ruby.network.ext_links0.int_node.port_buffers00.avg_stall_time 16771.557856
+system.ruby.network.ext_links0.int_node.port_buffers02.avg_buf_msgs 0.001160
+system.ruby.network.ext_links0.int_node.port_buffers02.avg_stall_time 121180.062406
+system.ruby.network.ext_links0.int_node.port_buffers04.avg_buf_msgs 0.001160
+system.ruby.network.ext_links0.int_node.port_buffers04.avg_stall_time 16749.523342
+system.ruby.network.ext_links0.int_node.port_buffers05.avg_buf_msgs 0.000010
+system.ruby.network.ext_links0.int_node.port_buffers05.avg_stall_time 3493.705161
+system.ruby.network.ext_links0.int_node.port_buffers07.avg_buf_msgs 0.001150
+system.ruby.network.ext_links0.int_node.port_buffers07.avg_stall_time 30490.654510
+system.ruby.network.ext_links0.int_node.port_buffers15.avg_buf_msgs 0.001150
+system.ruby.network.ext_links0.int_node.port_buffers15.avg_stall_time 30497.737889
+system.ruby.network.ext_links0.int_node.port_buffers17.avg_buf_msgs 0.000010
+system.ruby.network.ext_links0.int_node.port_buffers17.avg_stall_time 3490.277719
+system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 667407500
system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007895
system.ruby.network.ext_links0.int_node.msg_count.Control::0 1549
system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1549
system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112392
system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12296
system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12392
-system.ruby.network.ext_links1.int_node.port_buffers00.avg_buf_msgs 0.000010 # Average number of messages in buffer
-system.ruby.network.ext_links1.int_node.port_buffers00.avg_stall_time 3608.205673 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links1.int_node.port_buffers02.avg_buf_msgs 0.001150 # Average number of messages in buffer
-system.ruby.network.ext_links1.int_node.port_buffers02.avg_stall_time 31490.300903 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links1.int_node.port_buffers03.avg_buf_msgs 0.001150 # Average number of messages in buffer
-system.ruby.network.ext_links1.int_node.port_buffers03.avg_stall_time 15499.593577 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links1.int_node.port_buffers05.avg_buf_msgs 0.000010 # Average number of messages in buffer
-system.ruby.network.ext_links1.int_node.port_buffers05.avg_stall_time 1775.094697 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links1.int_node.port_buffers07.avg_buf_msgs 0.001150 # Average number of messages in buffer
-system.ruby.network.ext_links1.int_node.port_buffers07.avg_stall_time 15494.855841 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
+system.ruby.network.ext_links1.int_node.port_buffers00.avg_buf_msgs 0.000010
+system.ruby.network.ext_links1.int_node.port_buffers00.avg_stall_time 3608.205673
+system.ruby.network.ext_links1.int_node.port_buffers02.avg_buf_msgs 0.001150
+system.ruby.network.ext_links1.int_node.port_buffers02.avg_stall_time 31490.300903
+system.ruby.network.ext_links1.int_node.port_buffers03.avg_buf_msgs 0.001150
+system.ruby.network.ext_links1.int_node.port_buffers03.avg_stall_time 15499.593577
+system.ruby.network.ext_links1.int_node.port_buffers05.avg_buf_msgs 0.000010
+system.ruby.network.ext_links1.int_node.port_buffers05.avg_stall_time 1775.094697
+system.ruby.network.ext_links1.int_node.port_buffers07.avg_buf_msgs 0.001150
+system.ruby.network.ext_links1.int_node.port_buffers07.avg_stall_time 15494.855841
+system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 667407500
system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009908
system.ruby.network.ext_links1.int_node.msg_count.Control::0 14
system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535
system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664
system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 96
system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12280
-system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
-system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
-system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.tcp_cntrl0.L1cache.num_data_array_reads 8 # number of data array reads
-system.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes
-system.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads
-system.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes
-system.tcp_cntrl0.L1cache.num_data_array_stalls 6 # number of stalls caused by data array
-system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP
-system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl0.coalescer.gpu_ld_misses 2 # loads that miss in the GPU
-system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP
-system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl0.coalescer.gpu_st_misses 5 # stores that miss in the GPU
-system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU
-system.tcp_cntrl0.mandatoryQueue.avg_buf_msgs 0.000018 # Average number of messages in buffer
-system.tcp_cntrl0.mandatoryQueue.avg_stall_time 0.500256 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl0.probeToTCP.avg_buf_msgs 0.000006 # Average number of messages in buffer
-system.tcp_cntrl0.probeToTCP.avg_stall_time 680.485319 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl0.requestFromTCP.avg_buf_msgs 0.000430 # Average number of messages in buffer
-system.tcp_cntrl0.requestFromTCP.avg_stall_time 4552.451142 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl0.responseFromTCP.avg_buf_msgs 0.000479 # Average number of messages in buffer
-system.tcp_cntrl0.responseFromTCP.avg_stall_time 4534.171455 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl0.responseToTCP.avg_buf_msgs 0.000005 # Average number of messages in buffer
-system.tcp_cntrl0.responseToTCP.avg_stall_time 226.969283 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl0.unblockFromCore.avg_buf_msgs 0.000420 # Average number of messages in buffer
-system.tcp_cntrl0.unblockFromCore.avg_stall_time 4536.988325 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.ruby.network.ext_links2.int_node.port_buffers01.avg_buf_msgs 0.000006 # Average number of messages in buffer
-system.ruby.network.ext_links2.int_node.port_buffers01.avg_stall_time 623.782329 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links2.int_node.port_buffers03.avg_buf_msgs 0.000005 # Average number of messages in buffer
-system.ruby.network.ext_links2.int_node.port_buffers03.avg_stall_time 170.228086 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links2.int_node.port_buffers05.avg_buf_msgs 0.000004 # Average number of messages in buffer
-system.ruby.network.ext_links2.int_node.port_buffers05.avg_stall_time 555.902511 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links2.int_node.port_buffers07.avg_buf_msgs 0.000005 # Average number of messages in buffer
-system.ruby.network.ext_links2.int_node.port_buffers07.avg_stall_time 170.023563 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links2.int_node.port_buffers12.avg_buf_msgs 0.001150 # Average number of messages in buffer
-system.ruby.network.ext_links2.int_node.port_buffers12.avg_stall_time 31497.616524 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links2.int_node.port_buffers13.avg_buf_msgs 0.000013 # Average number of messages in buffer
-system.ruby.network.ext_links2.int_node.port_buffers13.avg_stall_time 4687.243604 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links2.int_node.port_buffers14.avg_buf_msgs 0.000010 # Average number of messages in buffer
-system.ruby.network.ext_links2.int_node.port_buffers14.avg_stall_time 3604.665857 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links2.int_node.port_buffers15.avg_buf_msgs 0.000010 # Average number of messages in buffer
-system.ruby.network.ext_links2.int_node.port_buffers15.avg_stall_time 4590.818257 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links2.int_node.port_buffers17.avg_buf_msgs 0.000013 # Average number of messages in buffer
-system.ruby.network.ext_links2.int_node.port_buffers17.avg_stall_time 4671.127513 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links2.int_node.port_buffers21.avg_buf_msgs 0.000002 # Average number of messages in buffer
-system.ruby.network.ext_links2.int_node.port_buffers21.avg_stall_time 171.646260 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links2.int_node.port_buffers22.avg_buf_msgs 0.000010 # Average number of messages in buffer
-system.ruby.network.ext_links2.int_node.port_buffers22.avg_stall_time 13808.776657 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links2.int_node.port_buffers24.avg_buf_msgs 0.001150 # Average number of messages in buffer
-system.ruby.network.ext_links2.int_node.port_buffers24.avg_stall_time 120469.035784 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links2.int_node.port_buffers26.avg_buf_msgs 0.000010 # Average number of messages in buffer
-system.ruby.network.ext_links2.int_node.port_buffers26.avg_stall_time 13752.445255 # Average number of cycles messages are stalled in this MB
-system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
+system.tcp_cntrl0.L1cache.demand_hits 0
+system.tcp_cntrl0.L1cache.demand_misses 0
+system.tcp_cntrl0.L1cache.demand_accesses 0
+system.tcp_cntrl0.L1cache.num_data_array_reads 8
+system.tcp_cntrl0.L1cache.num_data_array_writes 11
+system.tcp_cntrl0.L1cache.num_tag_array_reads 26
+system.tcp_cntrl0.L1cache.num_tag_array_writes 18
+system.tcp_cntrl0.L1cache.num_data_array_stalls 6
+system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 667407500
+system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2
+system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0
+system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0
+system.tcp_cntrl0.coalescer.gpu_ld_misses 2
+system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 4
+system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 0
+system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0
+system.tcp_cntrl0.coalescer.gpu_st_misses 5
+system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0
+system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0
+system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0
+system.tcp_cntrl0.coalescer.cp_ld_misses 0
+system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0
+system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0
+system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0
+system.tcp_cntrl0.coalescer.cp_st_misses 0
+system.tcp_cntrl0.mandatoryQueue.avg_buf_msgs 0.000018
+system.tcp_cntrl0.mandatoryQueue.avg_stall_time 0.500256
+system.tcp_cntrl0.probeToTCP.avg_buf_msgs 0.000006
+system.tcp_cntrl0.probeToTCP.avg_stall_time 680.485319
+system.tcp_cntrl0.requestFromTCP.avg_buf_msgs 0.000430
+system.tcp_cntrl0.requestFromTCP.avg_stall_time 4552.451142
+system.tcp_cntrl0.responseFromTCP.avg_buf_msgs 0.000479
+system.tcp_cntrl0.responseFromTCP.avg_stall_time 4534.171455
+system.tcp_cntrl0.responseToTCP.avg_buf_msgs 0.000005
+system.tcp_cntrl0.responseToTCP.avg_stall_time 226.969283
+system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500
+system.tcp_cntrl0.unblockFromCore.avg_buf_msgs 0.000420
+system.tcp_cntrl0.unblockFromCore.avg_stall_time 4536.988325
+system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500
+system.ruby.network.ext_links2.int_node.port_buffers01.avg_buf_msgs 0.000006
+system.ruby.network.ext_links2.int_node.port_buffers01.avg_stall_time 623.782329
+system.ruby.network.ext_links2.int_node.port_buffers03.avg_buf_msgs 0.000005
+system.ruby.network.ext_links2.int_node.port_buffers03.avg_stall_time 170.228086
+system.ruby.network.ext_links2.int_node.port_buffers05.avg_buf_msgs 0.000004
+system.ruby.network.ext_links2.int_node.port_buffers05.avg_stall_time 555.902511
+system.ruby.network.ext_links2.int_node.port_buffers07.avg_buf_msgs 0.000005
+system.ruby.network.ext_links2.int_node.port_buffers07.avg_stall_time 170.023563
+system.ruby.network.ext_links2.int_node.port_buffers12.avg_buf_msgs 0.001150
+system.ruby.network.ext_links2.int_node.port_buffers12.avg_stall_time 31497.616524
+system.ruby.network.ext_links2.int_node.port_buffers13.avg_buf_msgs 0.000013
+system.ruby.network.ext_links2.int_node.port_buffers13.avg_stall_time 4687.243604
+system.ruby.network.ext_links2.int_node.port_buffers14.avg_buf_msgs 0.000010
+system.ruby.network.ext_links2.int_node.port_buffers14.avg_stall_time 3604.665857
+system.ruby.network.ext_links2.int_node.port_buffers15.avg_buf_msgs 0.000010
+system.ruby.network.ext_links2.int_node.port_buffers15.avg_stall_time 4590.818257
+system.ruby.network.ext_links2.int_node.port_buffers17.avg_buf_msgs 0.000013
+system.ruby.network.ext_links2.int_node.port_buffers17.avg_stall_time 4671.127513
+system.ruby.network.ext_links2.int_node.port_buffers21.avg_buf_msgs 0.000002
+system.ruby.network.ext_links2.int_node.port_buffers21.avg_stall_time 171.646260
+system.ruby.network.ext_links2.int_node.port_buffers22.avg_buf_msgs 0.000010
+system.ruby.network.ext_links2.int_node.port_buffers22.avg_stall_time 13808.776657
+system.ruby.network.ext_links2.int_node.port_buffers24.avg_buf_msgs 0.001150
+system.ruby.network.ext_links2.int_node.port_buffers24.avg_stall_time 120469.035784
+system.ruby.network.ext_links2.int_node.port_buffers26.avg_buf_msgs 0.000010
+system.ruby.network.ext_links2.int_node.port_buffers26.avg_stall_time 13752.445255
+system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 667407500
system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000708
system.ruby.network.ext_links2.int_node.msg_count.Control::0 1535
system.ruby.network.ext_links2.int_node.msg_count.Control::1 14
system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 12200
system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 112
system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::5 136
-system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits
-system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses
-system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.tcp_cntrl1.L1cache.num_data_array_reads 8 # number of data array reads
-system.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes
-system.tcp_cntrl1.L1cache.num_tag_array_reads 25 # number of tag array reads
-system.tcp_cntrl1.L1cache.num_tag_array_writes 18 # number of tag array writes
-system.tcp_cntrl1.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array
-system.tcp_cntrl1.L1cache.num_data_array_stalls 6 # number of stalls caused by data array
-system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP
-system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2 # TCP to TCP load transfers
-system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP
-system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers
-system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl1.coalescer.gpu_st_misses 4 # stores that miss in the GPU
-system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP
-system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers
-system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC
-system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU
-system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP
-system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
-system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
-system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU
-system.tcp_cntrl1.mandatoryQueue.avg_buf_msgs 0.000024 # Average number of messages in buffer
-system.tcp_cntrl1.mandatoryQueue.avg_stall_time 0.662049 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl1.probeToTCP.avg_buf_msgs 0.000004 # Average number of messages in buffer
-system.tcp_cntrl1.probeToTCP.avg_stall_time 606.434608 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl1.requestFromTCP.avg_buf_msgs 0.000430 # Average number of messages in buffer
-system.tcp_cntrl1.requestFromTCP.avg_stall_time 4551.971675 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl1.responseFromTCP.avg_buf_msgs 0.000360 # Average number of messages in buffer
-system.tcp_cntrl1.responseFromTCP.avg_stall_time 4040.500048 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl1.responseToTCP.avg_buf_msgs 0.000005 # Average number of messages in buffer
-system.tcp_cntrl1.responseToTCP.avg_stall_time 226.696586 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.tcp_cntrl1.unblockFromCore.avg_buf_msgs 0.000420 # Average number of messages in buffer
-system.tcp_cntrl1.unblockFromCore.avg_stall_time 4531.534386 # Average number of cycles messages are stalled in this MB
-system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
-system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
-system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
-system.sqc_cntrl0.L1cache.num_data_array_reads 70 # number of data array reads
-system.sqc_cntrl0.L1cache.num_data_array_writes 3 # number of data array writes
-system.sqc_cntrl0.L1cache.num_tag_array_reads 70 # number of tag array reads
-system.sqc_cntrl0.L1cache.num_tag_array_writes 3 # number of tag array writes
-system.sqc_cntrl0.L1cache.num_data_array_stalls 28 # number of stalls caused by data array
-system.sqc_cntrl0.mandatoryQueue.avg_buf_msgs 0.000147 # Average number of messages in buffer
-system.sqc_cntrl0.mandatoryQueue.avg_stall_time 115.508892 # Average number of cycles messages are stalled in this MB
-system.sqc_cntrl0.requestFromSQC.avg_buf_msgs 0.000360 # Average number of messages in buffer
-system.sqc_cntrl0.requestFromSQC.avg_stall_time 9182.216368 # Average number of cycles messages are stalled in this MB
-system.sqc_cntrl0.responseToSQC.avg_buf_msgs 0.000002 # Average number of messages in buffer
-system.sqc_cntrl0.responseToSQC.avg_stall_time 228.860182 # Average number of cycles messages are stalled in this MB
-system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.sqc_cntrl0.sequencer.load_waiting_on_load 75 # Number of times a load aliased with a pending load
-system.sqc_cntrl0.unblockFromCore.avg_buf_msgs 0.000360 # Average number of messages in buffer
-system.sqc_cntrl0.unblockFromCore.avg_stall_time 9144.817927 # Average number of cycles messages are stalled in this MB
-system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
-system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses
-system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses
-system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits
-system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses
-system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses
-system.tccdir_cntrl0.directory.num_tag_array_reads 1552 # number of tag array reads
-system.tccdir_cntrl0.directory.num_tag_array_writes 25 # number of tag array writes
-system.tccdir_cntrl0.probeFromNB.avg_buf_msgs 0.001150 # Average number of messages in buffer
-system.tccdir_cntrl0.probeFromNB.avg_stall_time 31997.554717 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.probeToCore.avg_buf_msgs 0.000097 # Average number of messages in buffer
-system.tccdir_cntrl0.probeToCore.avg_stall_time 567.078591 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.requestFromTCP.avg_buf_msgs 0.001122 # Average number of messages in buffer
-system.tccdir_cntrl0.requestFromTCP.avg_stall_time 31695.077969 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.requestToNB.avg_buf_msgs 0.002517 # Average number of messages in buffer
-system.tccdir_cntrl0.requestToNB.avg_stall_time 13751.568729 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.responseFromNB.avg_buf_msgs 0.000010 # Average number of messages in buffer
-system.tccdir_cntrl0.responseFromNB.avg_stall_time 3661.858802 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.responseFromTCP.avg_buf_msgs 0.000010 # Average number of messages in buffer
-system.tccdir_cntrl0.responseFromTCP.avg_stall_time 4647.464310 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.responseToCore.avg_buf_msgs 0.000025 # Average number of messages in buffer
-system.tccdir_cntrl0.responseToCore.avg_stall_time 114.431589 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.responseToNB.avg_buf_msgs 0.275993 # Average number of messages in buffer
-system.tccdir_cntrl0.responseToNB.avg_stall_time 119969.254166 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.triggerQueue.avg_buf_msgs 0.000019 # Average number of messages in buffer
-system.tccdir_cntrl0.triggerQueue.avg_stall_time 113.351290 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.unblockFromTCP.avg_buf_msgs 0.000013 # Average number of messages in buffer
-system.tccdir_cntrl0.unblockFromTCP.avg_stall_time 4728.251535 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.unblockToNB.avg_buf_msgs 0.002517 # Average number of messages in buffer
-system.tccdir_cntrl0.unblockToNB.avg_stall_time 13695.471067 # Average number of cycles messages are stalled in this MB
-system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.ruby.network.int_link_buffers00.avg_buf_msgs 0.000010 # Average number of messages in buffer
-system.ruby.network.int_link_buffers00.avg_stall_time 3550.955792 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers02.avg_buf_msgs 0.001150 # Average number of messages in buffer
-system.ruby.network.int_link_buffers02.avg_stall_time 30990.478081 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers10.avg_buf_msgs 0.001150 # Average number of messages in buffer
-system.ruby.network.int_link_buffers10.avg_stall_time 30997.677581 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers12.avg_buf_msgs 0.000010 # Average number of messages in buffer
-system.ruby.network.int_link_buffers12.avg_stall_time 3547.472163 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers20.avg_buf_msgs 0.001150 # Average number of messages in buffer
-system.ruby.network.int_link_buffers20.avg_stall_time 15999.568480 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers22.avg_buf_msgs 0.000010 # Average number of messages in buffer
-system.ruby.network.int_link_buffers22.avg_stall_time 1832.343829 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers24.avg_buf_msgs 0.001150 # Average number of messages in buffer
-system.ruby.network.int_link_buffers24.avg_stall_time 15994.677914 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers30.avg_buf_msgs 0.000010 # Average number of messages in buffer
-system.ruby.network.int_link_buffers30.avg_stall_time 13865.983836 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers32.avg_buf_msgs 0.001150 # Average number of messages in buffer
-system.ruby.network.int_link_buffers32.avg_stall_time 120968.816653 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers34.avg_buf_msgs 0.000010 # Average number of messages in buffer
-system.ruby.network.int_link_buffers34.avg_stall_time 13809.418694 # Average number of cycles messages are stalled in this MB
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
+system.tcp_cntrl1.L1cache.demand_hits 0
+system.tcp_cntrl1.L1cache.demand_misses 0
+system.tcp_cntrl1.L1cache.demand_accesses 0
+system.tcp_cntrl1.L1cache.num_data_array_reads 8
+system.tcp_cntrl1.L1cache.num_data_array_writes 11
+system.tcp_cntrl1.L1cache.num_tag_array_reads 25
+system.tcp_cntrl1.L1cache.num_tag_array_writes 18
+system.tcp_cntrl1.L1cache.num_tag_array_stalls 2
+system.tcp_cntrl1.L1cache.num_data_array_stalls 6
+system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 667407500
+system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3
+system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2
+system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0
+system.tcp_cntrl1.coalescer.gpu_ld_misses 0
+system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 4
+system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 1
+system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0
+system.tcp_cntrl1.coalescer.gpu_st_misses 4
+system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0
+system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0
+system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0
+system.tcp_cntrl1.coalescer.cp_ld_misses 0
+system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0
+system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0
+system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0
+system.tcp_cntrl1.coalescer.cp_st_misses 0
+system.tcp_cntrl1.mandatoryQueue.avg_buf_msgs 0.000024
+system.tcp_cntrl1.mandatoryQueue.avg_stall_time 0.662049
+system.tcp_cntrl1.probeToTCP.avg_buf_msgs 0.000004
+system.tcp_cntrl1.probeToTCP.avg_stall_time 606.434608
+system.tcp_cntrl1.requestFromTCP.avg_buf_msgs 0.000430
+system.tcp_cntrl1.requestFromTCP.avg_stall_time 4551.971675
+system.tcp_cntrl1.responseFromTCP.avg_buf_msgs 0.000360
+system.tcp_cntrl1.responseFromTCP.avg_stall_time 4040.500048
+system.tcp_cntrl1.responseToTCP.avg_buf_msgs 0.000005
+system.tcp_cntrl1.responseToTCP.avg_stall_time 226.696586
+system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500
+system.tcp_cntrl1.unblockFromCore.avg_buf_msgs 0.000420
+system.tcp_cntrl1.unblockFromCore.avg_stall_time 4531.534386
+system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 667407500
+system.sqc_cntrl0.L1cache.demand_hits 0
+system.sqc_cntrl0.L1cache.demand_misses 0
+system.sqc_cntrl0.L1cache.demand_accesses 0
+system.sqc_cntrl0.L1cache.num_data_array_reads 70
+system.sqc_cntrl0.L1cache.num_data_array_writes 3
+system.sqc_cntrl0.L1cache.num_tag_array_reads 70
+system.sqc_cntrl0.L1cache.num_tag_array_writes 3
+system.sqc_cntrl0.L1cache.num_data_array_stalls 28
+system.sqc_cntrl0.mandatoryQueue.avg_buf_msgs 0.000147
+system.sqc_cntrl0.mandatoryQueue.avg_stall_time 115.508892
+system.sqc_cntrl0.requestFromSQC.avg_buf_msgs 0.000360
+system.sqc_cntrl0.requestFromSQC.avg_stall_time 9182.216368
+system.sqc_cntrl0.responseToSQC.avg_buf_msgs 0.000002
+system.sqc_cntrl0.responseToSQC.avg_stall_time 228.860182
+system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500
+system.sqc_cntrl0.sequencer.load_waiting_on_load 75
+system.sqc_cntrl0.unblockFromCore.avg_buf_msgs 0.000360
+system.sqc_cntrl0.unblockFromCore.avg_stall_time 9144.817927
+system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500
+system.tcc_cntrl0.L2cache.demand_hits 0
+system.tcc_cntrl0.L2cache.demand_misses 0
+system.tcc_cntrl0.L2cache.demand_accesses 0
+system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500
+system.tccdir_cntrl0.directory.demand_hits 0
+system.tccdir_cntrl0.directory.demand_misses 0
+system.tccdir_cntrl0.directory.demand_accesses 0
+system.tccdir_cntrl0.directory.num_tag_array_reads 1552
+system.tccdir_cntrl0.directory.num_tag_array_writes 25
+system.tccdir_cntrl0.probeFromNB.avg_buf_msgs 0.001150
+system.tccdir_cntrl0.probeFromNB.avg_stall_time 31997.554717
+system.tccdir_cntrl0.probeToCore.avg_buf_msgs 0.000097
+system.tccdir_cntrl0.probeToCore.avg_stall_time 567.078591
+system.tccdir_cntrl0.requestFromTCP.avg_buf_msgs 0.001122
+system.tccdir_cntrl0.requestFromTCP.avg_stall_time 31695.077969
+system.tccdir_cntrl0.requestToNB.avg_buf_msgs 0.002517
+system.tccdir_cntrl0.requestToNB.avg_stall_time 13751.568729
+system.tccdir_cntrl0.responseFromNB.avg_buf_msgs 0.000010
+system.tccdir_cntrl0.responseFromNB.avg_stall_time 3661.858802
+system.tccdir_cntrl0.responseFromTCP.avg_buf_msgs 0.000010
+system.tccdir_cntrl0.responseFromTCP.avg_stall_time 4647.464310
+system.tccdir_cntrl0.responseToCore.avg_buf_msgs 0.000025
+system.tccdir_cntrl0.responseToCore.avg_stall_time 114.431589
+system.tccdir_cntrl0.responseToNB.avg_buf_msgs 0.275993
+system.tccdir_cntrl0.responseToNB.avg_stall_time 119969.254166
+system.tccdir_cntrl0.triggerQueue.avg_buf_msgs 0.000019
+system.tccdir_cntrl0.triggerQueue.avg_stall_time 113.351290
+system.tccdir_cntrl0.unblockFromTCP.avg_buf_msgs 0.000013
+system.tccdir_cntrl0.unblockFromTCP.avg_stall_time 4728.251535
+system.tccdir_cntrl0.unblockToNB.avg_buf_msgs 0.002517
+system.tccdir_cntrl0.unblockToNB.avg_stall_time 13695.471067
+system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500
+system.ruby.network.int_link_buffers00.avg_buf_msgs 0.000010
+system.ruby.network.int_link_buffers00.avg_stall_time 3550.955792
+system.ruby.network.int_link_buffers02.avg_buf_msgs 0.001150
+system.ruby.network.int_link_buffers02.avg_stall_time 30990.478081
+system.ruby.network.int_link_buffers10.avg_buf_msgs 0.001150
+system.ruby.network.int_link_buffers10.avg_stall_time 30997.677581
+system.ruby.network.int_link_buffers12.avg_buf_msgs 0.000010
+system.ruby.network.int_link_buffers12.avg_stall_time 3547.472163
+system.ruby.network.int_link_buffers20.avg_buf_msgs 0.001150
+system.ruby.network.int_link_buffers20.avg_stall_time 15999.568480
+system.ruby.network.int_link_buffers22.avg_buf_msgs 0.000010
+system.ruby.network.int_link_buffers22.avg_stall_time 1832.343829
+system.ruby.network.int_link_buffers24.avg_buf_msgs 0.001150
+system.ruby.network.int_link_buffers24.avg_stall_time 15994.677914
+system.ruby.network.int_link_buffers30.avg_buf_msgs 0.000010
+system.ruby.network.int_link_buffers30.avg_stall_time 13865.983836
+system.ruby.network.int_link_buffers32.avg_buf_msgs 0.001150
+system.ruby.network.int_link_buffers32.avg_stall_time 120968.816653
+system.ruby.network.int_link_buffers34.avg_buf_msgs 0.000010
+system.ruby.network.int_link_buffers34.avg_stall_time 13809.418694
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 667407500
system.ruby.network.msg_count.Control 3112
system.ruby.network.msg_count.Request_Control 3115
system.ruby.network.msg_count.Response_Data 3153
system.ruby.network.msg_byte.Response_Data 227016
system.ruby.network.msg_byte.Response_Control 24592
system.ruby.network.msg_byte.Unblock_Control 24920
-system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks
-system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.sqc_coalescer.uncoalesced_accesses 70 # Number of uncoalesced TLB accesses
-system.sqc_coalescer.coalesced_accesses 50 # Number of coalesced TLB accesses
-system.sqc_coalescer.queuing_cycles 100000 # Number of cycles spent in queue
-system.sqc_coalescer.local_queuing_cycles 100000 # Number of cycles spent in queue for all incoming reqs
-system.sqc_coalescer.local_latency 1428.571429 # Avg. latency over all incoming pkts
-system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
-system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks
-system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
-system.sqc_tlb.local_TLB_accesses 50 # Number of TLB accesses
-system.sqc_tlb.local_TLB_hits 49 # Number of TLB hits
-system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses
-system.sqc_tlb.local_TLB_miss_rate 2 # TLB miss rate
-system.sqc_tlb.global_TLB_accesses 70 # Number of TLB accesses
-system.sqc_tlb.global_TLB_hits 62 # Number of TLB hits
-system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses
-system.sqc_tlb.global_TLB_miss_rate 11.428571 # TLB miss rate
-system.sqc_tlb.access_cycles 70008 # Cycles spent accessing this TLB level
-system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table
-system.sqc_tlb.unique_pages 1 # Number of unique pages touched
-system.sqc_tlb.local_cycles 50001 # Number of cycles spent in queue for all incoming reqs
-system.sqc_tlb.local_latency 1000.020000 # Avg. latency over incoming coalesced reqs
-system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states
+system.sqc_coalescer.clk_domain.voltage_domain.voltage 1
+system.sqc_coalescer.clk_domain.clock 1000
+system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500
+system.sqc_coalescer.uncoalesced_accesses 70
+system.sqc_coalescer.coalesced_accesses 50
+system.sqc_coalescer.queuing_cycles 100000
+system.sqc_coalescer.local_queuing_cycles 100000
+system.sqc_coalescer.local_latency 1428.571429
+system.sqc_tlb.clk_domain.voltage_domain.voltage 1
+system.sqc_tlb.clk_domain.clock 1000
+system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 667407500
+system.sqc_tlb.local_TLB_accesses 50
+system.sqc_tlb.local_TLB_hits 49
+system.sqc_tlb.local_TLB_misses 1
+system.sqc_tlb.local_TLB_miss_rate 2
+system.sqc_tlb.global_TLB_accesses 70
+system.sqc_tlb.global_TLB_hits 62
+system.sqc_tlb.global_TLB_misses 8
+system.sqc_tlb.global_TLB_miss_rate 11.428571
+system.sqc_tlb.access_cycles 70008
+system.sqc_tlb.page_table_cycles 0
+system.sqc_tlb.unique_pages 1
+system.sqc_tlb.local_cycles 50001
+system.sqc_tlb.local_latency 1000.020000
+system.sqc_tlb.avg_reuse_distance 0
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 667407500
system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005552
system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1549
system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12
projects / gem5.git / commitdiff