header_cycles=1
use_default_range=false
width=64
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
max_mem_size=268435456
mem_start_addr=0
system=system
pio=system.iobus.master[1]
-[system.realview.rtc_fake]
-type=AmbaFake
-amba_id=266289
-ignore_access=false
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+gic=system.realview.gic
+int_delay=100000
+int_num=42
pio_addr=268529664
pio_latency=1000
system=system
+time=Thu Jan 1 00:00:00 2009
pio=system.iobus.master[23]
[system.realview.sci_fake]
warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
-warn: 5655885500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
-warn: 5665876500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
-warn: 5705833500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
-warn: 5722480500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
-warn: 6171915000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
+warn: 5654850500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
+warn: 5664849500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
+warn: 5704830500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
+warn: 5721485500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
warn: LCD dual screen mode not supported
-warn: 53400472000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
+warn: 53386624000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:47:04
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 18:15:21
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker
-The currently selected ARM platforms doesn't support
- the amount of DRAM you've selected. Please try
- another platform
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2503099557500 because m5_exit instruction encountered
+Exiting @ tick 2501676293500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.503100 # Number of seconds simulated
-sim_ticks 2503099557500 # Number of ticks simulated
-final_tick 2503099557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.501676 # Number of seconds simulated
+sim_ticks 2501676293500 # Number of ticks simulated
+final_tick 2501676293500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 68083 # Simulator instruction rate (inst/s)
-host_op_rate 87941 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2866621111 # Simulator tick rate (ticks/s)
-host_mem_usage 384248 # Number of bytes of host memory used
-host_seconds 873.19 # Real time elapsed on the host
-sim_insts 59449445 # Number of instructions simulated
-sim_ops 76789092 # Number of ops (including micro ops) simulated
+host_inst_rate 79857 # Simulator instruction rate (inst/s)
+host_op_rate 103150 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3360326389 # Simulator tick rate (ticks/s)
+host_mem_usage 381664 # Number of bytes of host memory used
+host_seconds 744.47 # Real time elapsed on the host
+sim_insts 59451291 # Number of instructions simulated
+sim_ops 76792341 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read 130740776 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 1120320 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 9586312 # Number of bytes written to this memory
-system.physmem.num_reads 15115704 # Number of read requests responded to by this memory
-system.physmem.num_writes 856678 # Number of write requests responded to by this memory
+system.physmem.bytes_read 129652968 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1121024 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 9585096 # Number of bytes written to this memory
+system.physmem.num_reads 14979455 # Number of read requests responded to by this memory
+system.physmem.num_writes 856659 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 52231553 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 447573 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 3829777 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 56061329 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 119794 # number of replacements
-system.l2c.tagsinuse 26073.611012 # Cycle average of tags in use
-system.l2c.total_refs 1840774 # Total number of references to valid blocks.
-system.l2c.sampled_refs 150725 # Sample count of references to valid blocks.
-system.l2c.avg_refs 12.212798 # Average number of references to valid blocks.
+system.physmem.bw_read 51826437 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 448109 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 3831469 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 55657906 # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 119784 # number of replacements
+system.l2c.tagsinuse 25999.615357 # Cycle average of tags in use
+system.l2c.total_refs 1826145 # Total number of references to valid blocks.
+system.l2c.sampled_refs 150763 # Sample count of references to valid blocks.
+system.l2c.avg_refs 12.112687 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 14308.761179 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker 64.610993 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker 0.928498 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst 6189.887268 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data 5509.423074 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.218334 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker 0.000986 # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks 14272.421964 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker 65.344146 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker 0.932012 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst 6169.201034 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data 5491.716201 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.217780 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker 0.000997 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker 0.000014 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst 0.094450 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data 0.084067 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.397852 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker 152848 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker 11656 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst 998872 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data 377319 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1540695 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 633173 # number of Writeback hits
-system.l2c.Writeback_hits::total 633173 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data 44 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 44 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu.data 5 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data 105891 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 105891 # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker 152848 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker 11656 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst 998872 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data 483210 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1646586 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker 152848 # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker 11656 # number of overall hits
-system.l2c.overall_hits::cpu.inst 998872 # number of overall hits
-system.l2c.overall_hits::cpu.data 483210 # number of overall hits
-system.l2c.overall_hits::total 1646586 # number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker 147 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.itb.walker 12 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst 17382 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data 19146 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 36687 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data 3313 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 3313 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data 140346 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 140346 # number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker 147 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.itb.walker 12 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst 17382 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data 159492 # number of demand (read+write) misses
-system.l2c.demand_misses::total 177033 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker 147 # number of overall misses
-system.l2c.overall_misses::cpu.itb.walker 12 # number of overall misses
-system.l2c.overall_misses::cpu.inst 17382 # number of overall misses
-system.l2c.overall_misses::cpu.data 159492 # number of overall misses
-system.l2c.overall_misses::total 177033 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker 7686500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.itb.walker 617000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst 910008500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data 1001033000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 1919345000 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data 1206000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 1206000 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data 7379766500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 7379766500 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker 7686500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.itb.walker 617000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst 910008500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data 8380799500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 9299111500 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker 7686500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.itb.walker 617000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst 910008500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data 8380799500 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 9299111500 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker 152995 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker 11668 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst 1016254 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data 396465 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1577382 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 633173 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 633173 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data 3357 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 3357 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data 246237 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 246237 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker 152995 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker 11668 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst 1016254 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data 642702 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1823619 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker 152995 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker 11668 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst 1016254 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data 642702 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1823619 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000961 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001028 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst 0.017104 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data 0.048292 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data 0.986893 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data 0.569963 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker 0.000961 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker 0.001028 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst 0.017104 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data 0.248159 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker 0.000961 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.itb.walker 0.001028 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst 0.017104 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data 0.248159 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52289.115646 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 51416.666667 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52353.497871 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52284.184686 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data 364.020525 # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52582.663560 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52289.115646 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.itb.walker 51416.666667 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 52353.497871 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52546.833070 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52289.115646 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.itb.walker 51416.666667 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 52353.497871 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52546.833070 # average overall miss latency
+system.l2c.occ_percent::cpu.inst 0.094135 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data 0.083797 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.396723 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker 141919 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker 12116 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst 995766 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data 377927 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1527728 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 634955 # number of Writeback hits
+system.l2c.Writeback_hits::total 634955 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data 46 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 46 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu.data 7 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data 105770 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 105770 # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker 141919 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker 12116 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst 995766 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data 483697 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1633498 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker 141919 # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker 12116 # number of overall hits
+system.l2c.overall_hits::cpu.inst 995766 # number of overall hits
+system.l2c.overall_hits::cpu.data 483697 # number of overall hits
+system.l2c.overall_hits::total 1633498 # number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker 157 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker 13 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst 17392 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data 19166 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 36728 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data 3302 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 3302 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data 140335 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 140335 # number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker 157 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker 13 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst 17392 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data 159501 # number of demand (read+write) misses
+system.l2c.demand_misses::total 177063 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker 157 # number of overall misses
+system.l2c.overall_misses::cpu.itb.walker 13 # number of overall misses
+system.l2c.overall_misses::cpu.inst 17392 # number of overall misses
+system.l2c.overall_misses::cpu.data 159501 # number of overall misses
+system.l2c.overall_misses::total 177063 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker 8196500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.itb.walker 677000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst 910933000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data 1001503500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 1921310000 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data 1203000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 1203000 # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data 7367598500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 7367598500 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker 8196500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.itb.walker 677000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst 910933000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data 8369102000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 9288908500 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker 8196500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.itb.walker 677000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.inst 910933000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data 8369102000 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 9288908500 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker 142076 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker 12129 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst 1013158 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data 397093 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1564456 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 634955 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 634955 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data 3348 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 3348 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu.data 10 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data 246105 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 246105 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker 142076 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker 12129 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst 1013158 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data 643198 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1810561 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker 142076 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker 12129 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst 1013158 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data 643198 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1810561 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001105 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001072 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst 0.017166 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data 0.048266 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data 0.986260 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.300000 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data 0.570224 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker 0.001105 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker 0.001072 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst 0.017166 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data 0.247981 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker 0.001105 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker 0.001072 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst 0.017166 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data 0.247981 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52207.006369 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52076.923077 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52376.552438 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52254.174058 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data 364.324652 # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52500.078384 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52207.006369 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.itb.walker 52076.923077 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52376.552438 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52470.529965 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52207.006369 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.itb.walker 52076.923077 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52376.552438 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52470.529965 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 102660 # number of writebacks
-system.l2c.writebacks::total 102660 # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu.itb.walker 1 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu.itb.walker 1 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu.data 79 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu.itb.walker 1 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu.data 79 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 93 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 147 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.itb.walker 11 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst 17369 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data 19067 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 36594 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data 3313 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 3313 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data 140346 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 140346 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.dtb.walker 147 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.itb.walker 11 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst 17369 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data 159413 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 176940 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.dtb.walker 147 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.itb.walker 11 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst 17369 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data 159413 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 176940 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 5904000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 442000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst 697218500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data 765075000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 1468639500 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 133817000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 133817000 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5636526500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 5636526500 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 5904000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.itb.walker 442000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst 697218500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data 6401601500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 7105166000 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 5904000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.itb.walker 442000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst 697218500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data 6401601500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 7105166000 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5507000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131763880500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131769387500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32348463263 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 32348463263 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5507000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data 164112343763 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 164117850763 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048093 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986893 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569963 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data 0.248036 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data 0.248036 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40141.545282 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40125.609692 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40391.488077 # average UpgradeReq mshr miss latency
+system.l2c.writebacks::writebacks 102641 # number of writebacks
+system.l2c.writebacks::total 102641 # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu.data 81 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu.data 81 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total 91 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 157 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.itb.walker 13 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst 17382 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data 19085 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 36637 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data 3302 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 3302 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data 140335 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 140335 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker 157 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.itb.walker 13 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst 17382 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data 159420 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 176972 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker 157 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.itb.walker 13 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst 17382 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data 159420 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 176972 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 6288500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 521000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst 698170500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data 765243500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 1470223500 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 132738500 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 132738500 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5623589000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 5623589000 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 6288500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.itb.walker 521000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst 698170500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data 6388832500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 7093812500 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 6288500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.itb.walker 521000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst 698170500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data 6388832500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 7093812500 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5427000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131765321500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131770748500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32346079731 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 32346079731 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5427000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data 164111401231 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 164116828231 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001105 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001072 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017156 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048062 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986260 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.300000 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.570224 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001105 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001072 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst 0.017156 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data 0.247855 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001105 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001072 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst 0.017156 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data 0.247855 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40076.923077 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40166.292717 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.594184 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40199.424591 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40161.646930 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40141.545282 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40157.336604 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40141.545282 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40157.336604 # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40072.604838 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40076.923077 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40166.292717 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.476728 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40076.923077 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40166.292717 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.476728 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 15016256 # DTB read hits
-system.cpu.checker.dtb.read_misses 7312 # DTB read misses
-system.cpu.checker.dtb.write_hits 11274185 # DTB write hits
-system.cpu.checker.dtb.write_misses 2190 # DTB write misses
+system.cpu.checker.dtb.read_hits 15017081 # DTB read hits
+system.cpu.checker.dtb.read_misses 7305 # DTB read misses
+system.cpu.checker.dtb.write_hits 11274838 # DTB write hits
+system.cpu.checker.dtb.write_misses 2191 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults 177 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 15023568 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11276375 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 15024386 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11277029 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26290441 # DTB hits
-system.cpu.checker.dtb.misses 9502 # DTB misses
-system.cpu.checker.dtb.accesses 26299943 # DTB accesses
-system.cpu.checker.itb.inst_hits 60615999 # ITB inst hits
+system.cpu.checker.dtb.hits 26291919 # DTB hits
+system.cpu.checker.dtb.misses 9496 # DTB misses
+system.cpu.checker.dtb.accesses 26301415 # DTB accesses
+system.cpu.checker.itb.inst_hits 60617853 # ITB inst hits
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 60620470 # ITB inst accesses
-system.cpu.checker.itb.hits 60615999 # DTB hits
+system.cpu.checker.itb.inst_accesses 60622324 # ITB inst accesses
+system.cpu.checker.itb.hits 60617853 # DTB hits
system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 60620470 # DTB accesses
-system.cpu.checker.numCycles 77067453 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 60622324 # DTB accesses
+system.cpu.checker.numCycles 77070710 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51948606 # DTB read hits
-system.cpu.dtb.read_misses 101816 # DTB read misses
-system.cpu.dtb.write_hits 11910706 # DTB write hits
-system.cpu.dtb.write_misses 24423 # DTB write misses
+system.cpu.dtb.read_hits 52069399 # DTB read hits
+system.cpu.dtb.read_misses 92258 # DTB read misses
+system.cpu.dtb.write_hits 11926847 # DTB write hits
+system.cpu.dtb.write_misses 25023 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 7999 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 5598 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 665 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 8152 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 5662 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 693 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 2849 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 52050422 # DTB read accesses
-system.cpu.dtb.write_accesses 11935129 # DTB write accesses
+system.cpu.dtb.perms_faults 2731 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 52161657 # DTB read accesses
+system.cpu.dtb.write_accesses 11951870 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63859312 # DTB hits
-system.cpu.dtb.misses 126239 # DTB misses
-system.cpu.dtb.accesses 63985551 # DTB accesses
-system.cpu.itb.inst_hits 13611127 # ITB inst hits
-system.cpu.itb.inst_misses 11794 # ITB inst misses
+system.cpu.dtb.hits 63996246 # DTB hits
+system.cpu.dtb.misses 117281 # DTB misses
+system.cpu.dtb.accesses 64113527 # DTB accesses
+system.cpu.itb.inst_hits 13699541 # ITB inst hits
+system.cpu.itb.inst_misses 12131 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 5224 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 5248 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 6917 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 6936 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 13622921 # ITB inst accesses
-system.cpu.itb.hits 13611127 # DTB hits
-system.cpu.itb.misses 11794 # DTB misses
-system.cpu.itb.accesses 13622921 # DTB accesses
-system.cpu.numCycles 414035717 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 13711672 # ITB inst accesses
+system.cpu.itb.hits 13699541 # DTB hits
+system.cpu.itb.misses 12131 # DTB misses
+system.cpu.itb.accesses 13711672 # DTB accesses
+system.cpu.numCycles 411150559 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 15526652 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 12489737 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 928336 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 10678484 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 8212324 # Number of BTB hits
+system.cpu.BPredUnit.lookups 15631672 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 12342234 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 929456 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 10552810 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 8288947 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1312295 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 195061 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 32929499 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 102163781 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 15526652 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9524619 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 22440538 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6579937 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 148688 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 93080203 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2936 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 137545 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 217702 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13603433 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 995292 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6599 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 153452703 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.827416 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.209875 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1323523 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 194787 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 32982972 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 102837345 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 15631672 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9612470 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 22590084 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6692504 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 158663 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 89850563 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2746 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 143204 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 218934 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 483 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 13691858 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 996334 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6838 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 150553763 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.848436 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.233477 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 131028378 85.39% 85.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1463837 0.95% 86.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1832687 1.19% 87.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2690815 1.75% 89.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1870921 1.22% 90.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1178749 0.77% 91.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2936419 1.91% 93.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 835625 0.54% 93.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9615272 6.27% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 127980574 85.01% 85.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1480097 0.98% 85.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1855620 1.23% 87.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2694532 1.79% 89.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1893570 1.26% 90.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1188011 0.79% 91.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2948135 1.96% 93.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 848652 0.56% 93.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 9664572 6.42% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 153452703 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.037501 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.246751 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 34954549 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 92988756 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 20078806 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1116855 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 4313737 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2248287 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 185454 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 119076129 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 599477 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 4313737 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 37045133 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36926846 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 49909637 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 19098925 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6158425 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 111441141 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 3427 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 975111 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4036126 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 44783 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 115828569 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 512776978 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 512681517 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 95461 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 77492759 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 38335809 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1177287 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1072928 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13010963 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 21488170 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 14015818 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1893787 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2361029 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 101216530 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1853504 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 125772492 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 220452 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 25469081 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 69618284 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 353864 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 153452703 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.819617 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.525568 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 150553763 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.038019 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.250121 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 35091688 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 89690975 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 20321625 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1025705 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4423770 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2273029 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 186320 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 119828190 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 605140 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 4423770 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 37165531 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37166387 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 46484492 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 19226681 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6086902 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 112339029 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 3754 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1012932 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4107831 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 44905 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 116884712 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 516607430 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 516512877 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 94553 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 77495227 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 39389484 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 939636 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 835400 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12435347 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 21635443 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 14050113 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1939177 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2494760 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 102209700 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1618930 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 126189021 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 231742 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 26205661 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 71388624 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 331981 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 150553763 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.838166 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.542583 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 107878797 70.30% 70.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 14731235 9.60% 79.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7302555 4.76% 84.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5766685 3.76% 88.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12704866 8.28% 96.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2797979 1.82% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1703854 1.11% 99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 430247 0.28% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 136485 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 105343416 69.97% 69.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 14065037 9.34% 79.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7354541 4.88% 84.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5909522 3.93% 88.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12758140 8.47% 96.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2807768 1.86% 98.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1730475 1.15% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 446826 0.30% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 138038 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 153452703 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 150553763 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 55588 0.63% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 3 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8410763 94.57% 95.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 427006 4.80% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 60599 0.68% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8416262 94.64% 95.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 416317 4.68% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 59380040 47.21% 47.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 95959 0.08% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 34 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 46 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2266 0.00% 47.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.38% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 53622551 42.63% 90.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12565056 9.99% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 59665616 47.28% 47.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 95635 0.08% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 36 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 48 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2270 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 53732100 42.58% 90.03% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12586768 9.97% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 125772492 # Type of FU issued
-system.cpu.iq.rate 0.303772 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8893360 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.070710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 414213065 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 128557320 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 86496982 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 24084 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 13214 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10457 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 134546484 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12838 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 592105 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 126189021 # Type of FU issued
+system.cpu.iq.rate 0.306917 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8893180 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.070475 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 412149363 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 130053896 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 86886822 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 24048 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 13080 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10409 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 134962848 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12823 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 636825 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5807721 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 11311 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 32412 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2237013 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 5953964 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 11249 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 33793 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2270680 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34115378 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1150417 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34115287 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1151875 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 4313737 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28451597 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 431255 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 103286909 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 337253 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 21488170 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 14015818 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1227531 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 94319 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 11225 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 32412 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 548239 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 349587 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 897826 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 122535537 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52641416 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3236955 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 4423770 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 28606306 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 435959 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 104089793 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 334839 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 21635443 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 14050113 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 991881 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 95881 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 11592 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 33793 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 550966 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 345374 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 896340 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 122956903 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52760819 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3232118 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 216875 # number of nop insts executed
-system.cpu.iew.exec_refs 65061832 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11533456 # Number of branches executed
-system.cpu.iew.exec_stores 12420416 # Number of stores executed
-system.cpu.iew.exec_rate 0.295954 # Inst execution rate
-system.cpu.iew.wb_sent 121007788 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 86507439 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 46901063 # num instructions producing a value
-system.cpu.iew.wb_consumers 86866563 # num instructions consuming a value
+system.cpu.iew.exec_nop 261163 # number of nop insts executed
+system.cpu.iew.exec_refs 65197273 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11589071 # Number of branches executed
+system.cpu.iew.exec_stores 12436454 # Number of stores executed
+system.cpu.iew.exec_rate 0.299056 # Inst execution rate
+system.cpu.iew.wb_sent 121403477 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 86897231 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47438485 # num instructions producing a value
+system.cpu.iew.wb_consumers 88321921 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.208937 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.539921 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.211351 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.537109 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 59599826 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 76939473 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 26171914 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1499640 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 790317 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 149221313 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.515606 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.482610 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 59601672 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 76942722 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 26965943 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1286949 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 790517 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 146212348 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.526240 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.505087 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 120951257 81.05% 81.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 14347270 9.61% 90.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4034652 2.70% 93.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2127712 1.43% 94.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1768055 1.18% 95.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1033434 0.69% 96.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1556613 1.04% 97.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 657865 0.44% 98.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2744455 1.84% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 118498573 81.05% 81.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13699176 9.37% 90.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3966547 2.71% 93.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2244227 1.53% 94.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1750329 1.20% 95.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1033206 0.71% 96.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1542131 1.05% 97.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 667633 0.46% 98.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2810526 1.92% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 149221313 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 59599826 # Number of instructions committed
-system.cpu.commit.committedOps 76939473 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 146212348 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 59601672 # Number of instructions committed
+system.cpu.commit.committedOps 76942722 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27459254 # Number of memory references committed
-system.cpu.commit.loads 15680449 # Number of loads committed
-system.cpu.commit.membars 413031 # Number of memory barriers committed
-system.cpu.commit.branches 9890920 # Number of branches committed
+system.cpu.commit.refs 27460912 # Number of memory references committed
+system.cpu.commit.loads 15681479 # Number of loads committed
+system.cpu.commit.membars 413077 # Number of memory barriers committed
+system.cpu.commit.branches 9891359 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 68492585 # Number of committed integer instructions.
-system.cpu.commit.function_calls 995546 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2744455 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 68495555 # Number of committed integer instructions.
+system.cpu.commit.function_calls 995632 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2810526 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 247831805 # The number of ROB reads
-system.cpu.rob.rob_writes 210661614 # The number of ROB writes
-system.cpu.timesIdled 1891867 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 260583014 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4592075418 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 59449445 # Number of Instructions Simulated
-system.cpu.committedOps 76789092 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 59449445 # Number of Instructions Simulated
-system.cpu.cpi 6.964501 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 6.964501 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.143585 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.143585 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 555570057 # number of integer regfile reads
-system.cpu.int_regfile_writes 88783659 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8868 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2963 # number of floating regfile writes
-system.cpu.misc_regfile_reads 134383864 # number of misc regfile reads
-system.cpu.misc_regfile_writes 912266 # number of misc regfile writes
-system.cpu.icache.replacements 1016880 # number of replacements
-system.cpu.icache.tagsinuse 511.619498 # Cycle average of tags in use
-system.cpu.icache.total_refs 12495254 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1017392 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 12.281652 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 6291400000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.619498 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.999257 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.999257 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 12495254 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 12495254 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 12495254 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 12495254 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 12495254 # number of overall hits
-system.cpu.icache.overall_hits::total 12495254 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1108036 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1108036 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1108036 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1108036 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1108036 # number of overall misses
-system.cpu.icache.overall_misses::total 1108036 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 16316535479 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 16316535479 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 16316535479 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 16316535479 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 16316535479 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 16316535479 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 13603290 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 13603290 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 13603290 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 13603290 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 13603290 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 13603290 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081454 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.081454 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.081454 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14725.636603 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14725.636603 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14725.636603 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 2951482 # number of cycles access was blocked
+system.cpu.rob.rob_reads 245553933 # The number of ROB reads
+system.cpu.rob.rob_writes 212368242 # The number of ROB writes
+system.cpu.timesIdled 1894262 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 260596796 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4592114044 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 59451291 # Number of Instructions Simulated
+system.cpu.committedOps 76792341 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 59451291 # Number of Instructions Simulated
+system.cpu.cpi 6.915755 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 6.915755 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.144597 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.144597 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 557431991 # number of integer regfile reads
+system.cpu.int_regfile_writes 89182975 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8912 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2994 # number of floating regfile writes
+system.cpu.misc_regfile_reads 135303561 # number of misc regfile reads
+system.cpu.misc_regfile_writes 912352 # number of misc regfile writes
+system.cpu.icache.replacements 1013837 # number of replacements
+system.cpu.icache.tagsinuse 511.616166 # Cycle average of tags in use
+system.cpu.icache.total_refs 12585526 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 1014349 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 12.407491 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 6289783000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 511.616166 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.999250 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.999250 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 12585526 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 12585526 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 12585526 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 12585526 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 12585526 # number of overall hits
+system.cpu.icache.overall_hits::total 12585526 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1106194 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1106194 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1106194 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1106194 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1106194 # number of overall misses
+system.cpu.icache.overall_misses::total 1106194 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 16291440480 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 16291440480 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 16291440480 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 16291440480 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 16291440480 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 16291440480 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 13691720 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 13691720 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 13691720 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 13691720 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 13691720 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 13691720 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080793 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.080793 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.080793 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14727.471384 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14727.471384 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14727.471384 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 3199983 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 405 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 416 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 7287.609877 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 7692.266827 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks::writebacks 58719 # number of writebacks
-system.cpu.icache.writebacks::total 58719 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90611 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 90611 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 90611 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 90611 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 90611 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 90611 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1017425 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1017425 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1017425 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1017425 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1017425 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1017425 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12153604482 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 12153604482 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12153604482 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 12153604482 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12153604482 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 12153604482 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7398500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7398500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7398500 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total 7398500 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11945.454930 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11945.454930 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11945.454930 # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks 59844 # number of writebacks
+system.cpu.icache.writebacks::total 59844 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91810 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 91810 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 91810 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 91810 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 91810 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 91810 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1014384 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 1014384 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 1014384 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 1014384 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 1014384 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 1014384 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12127535483 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 12127535483 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12127535483 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 12127535483 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12127535483 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 12127535483 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7292000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074087 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074087 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074087 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11955.566613 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11955.566613 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11955.566613 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 644925 # number of replacements
-system.cpu.dcache.tagsinuse 511.991557 # Cycle average of tags in use
-system.cpu.dcache.total_refs 21957407 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 645437 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 34.019443 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 49249000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.991557 # Average occupied blocks per requestor
+system.cpu.dcache.replacements 645435 # number of replacements
+system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use
+system.cpu.dcache.total_refs 22022963 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 645947 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 34.094071 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 49188000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.991565 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 14117520 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 14117520 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 7264910 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 7264910 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 285961 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 285961 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 285492 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 285492 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 21382430 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 21382430 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 21382430 # number of overall hits
-system.cpu.dcache.overall_hits::total 21382430 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 735373 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 735373 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2966010 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2966010 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 13726 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 13726 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 3701383 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3701383 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3701383 # number of overall misses
-system.cpu.dcache.overall_misses::total 3701383 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11086457500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11086457500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 110422837752 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 110422837752 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223704000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 223704000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 187500 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 187500 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 121509295252 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 121509295252 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 121509295252 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 121509295252 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 14852893 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 14852893 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10230920 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10230920 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299687 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 299687 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 285500 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 285500 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 25083813 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 25083813 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 25083813 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 25083813 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049510 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289906 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045801 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000028 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.147561 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.147561 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15075.964850 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37229.421935 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.828938 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 23437.500000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32828.079464 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32828.079464 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 16342936 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 7612500 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2868 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 5698.373780 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 28404.850746 # average number of cycles each access was blocked
+system.cpu.dcache.ReadReq_hits::cpu.data 14182326 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 14182326 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 7265741 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 7265741 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 285851 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 285851 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 285519 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 285519 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 21448067 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 21448067 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 21448067 # number of overall hits
+system.cpu.dcache.overall_hits::total 21448067 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 745935 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 745935 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2965804 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2965804 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 13758 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 13758 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 10 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 3711739 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3711739 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3711739 # number of overall misses
+system.cpu.dcache.overall_misses::total 3711739 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11230893500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 11230893500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 110142219264 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 110142219264 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224423500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 224423500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 267500 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 267500 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 121373112764 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 121373112764 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 121373112764 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 121373112764 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 14928261 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 14928261 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10231545 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10231545 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299609 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 299609 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 285529 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 285529 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 25159806 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 25159806 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 25159806 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 25159806 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049968 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289869 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045920 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000035 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.147527 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.147527 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15056.128885 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37137.389815 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16312.218346 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26750 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32699.797255 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32699.797255 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 16852944 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 7563500 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2993 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 267 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 5630.786502 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 28327.715356 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 574454 # number of writebacks
-system.cpu.dcache.writebacks::total 574454 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 348401 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 348401 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716534 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2716534 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1379 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1379 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3064935 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3064935 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3064935 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3064935 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386972 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 386972 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249476 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 249476 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12347 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12347 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 636448 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 636448 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 636448 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 636448 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5265104500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 5265104500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8925107436 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8925107436 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165722000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165722000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14190211936 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 14190211936 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14190211936 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 14190211936 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147157757000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147157757000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42274928970 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42274928970 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189432685970 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 189432685970 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026054 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024385 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041200 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025373 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025373 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13605.905595 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35775.415014 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13422.045841 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20312.500000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 575111 # number of writebacks
+system.cpu.dcache.writebacks::total 575111 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358347 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 358347 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716460 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2716460 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1395 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1395 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3074807 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3074807 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3074807 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3074807 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387588 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 387588 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249344 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 249344 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12363 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12363 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 10 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 636932 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 636932 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 636932 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 636932 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5281773000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 5281773000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8909514444 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8909514444 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 166180500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 166180500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 235000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 235000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14191287444 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 14191287444 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14191287444 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 14191287444 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147159264500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147159264500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42252638495 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42252638495 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189411902995 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 189411902995 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025963 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024370 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041264 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025315 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025315 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13627.287223 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35731.818067 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13441.761708 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23500 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22280.694712 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22280.694712 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1307788731818 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1307788731818 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1296055922339 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1296055922339 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 87981 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 87985 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
header_cycles=1
use_default_range=false
width=64
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
max_mem_size=268435456
mem_start_addr=0
system=system
pio=system.iobus.master[1]
-[system.realview.rtc_fake]
-type=AmbaFake
-amba_id=266289
-ignore_access=false
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+gic=system.realview.gic
+int_delay=100000
+int_num=42
pio_addr=268529664
pio_latency=1000
system=system
+time=Thu Jan 1 00:00:00 2009
pio=system.iobus.master[23]
[system.realview.sci_fake]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:49:08
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 18:22:04
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual
-The currently selected ARM platforms doesn't support
- the amount of DRAM you've selected. Please try
- another platform
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2572151538500 because m5_exit instruction encountered
+Exiting @ tick 2570828403500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.572152 # Number of seconds simulated
-sim_ticks 2572151538500 # Number of ticks simulated
-final_tick 2572151538500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.570828 # Number of seconds simulated
+sim_ticks 2570828403500 # Number of ticks simulated
+final_tick 2570828403500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 81031 # Simulator instruction rate (inst/s)
-host_op_rate 104662 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3370719075 # Simulator tick rate (ticks/s)
-host_mem_usage 387768 # Number of bytes of host memory used
-host_seconds 763.09 # Real time elapsed on the host
-sim_insts 61833482 # Number of instructions simulated
-sim_ops 79866272 # Number of ops (including micro ops) simulated
+host_inst_rate 96885 # Simulator instruction rate (inst/s)
+host_op_rate 125154 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4026902595 # Simulator tick rate (ticks/s)
+host_mem_usage 385208 # Number of bytes of host memory used
+host_seconds 638.41 # Real time elapsed on the host
+sim_insts 61852501 # Number of instructions simulated
+sim_ops 79899751 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read 131401380 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 1182400 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 10205328 # Number of bytes written to this memory
-system.physmem.num_reads 15127677 # Number of read requests responded to by this memory
-system.physmem.num_writes 869412 # Number of write requests responded to by this memory
+system.physmem.bytes_read 131418468 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1192320 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 10172560 # Number of bytes written to this memory
+system.physmem.num_reads 15127944 # Number of read requests responded to by this memory
+system.physmem.num_writes 868900 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 51086174 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 459693 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 3967623 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 55053797 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 130950 # number of replacements
-system.l2c.tagsinuse 27519.569663 # Cycle average of tags in use
-system.l2c.total_refs 1851108 # Total number of references to valid blocks.
-system.l2c.sampled_refs 160575 # Sample count of references to valid blocks.
-system.l2c.avg_refs 11.527996 # Average number of references to valid blocks.
+system.physmem.bw_read 51119113 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 463788 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 3956919 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 55076032 # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 130877 # number of replacements
+system.l2c.tagsinuse 27573.095607 # Cycle average of tags in use
+system.l2c.total_refs 1846037 # Total number of references to valid blocks.
+system.l2c.sampled_refs 160860 # Sample count of references to valid blocks.
+system.l2c.avg_refs 11.476047 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 15169.344330 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker 19.734111 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker 0.051736 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 2916.125169 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 1448.526960 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker 25.001568 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.itb.walker 0.040261 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 3299.000824 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 4641.744705 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.231466 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.dtb.walker 0.000301 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.044497 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.022103 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.dtb.walker 0.000381 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.itb.walker 0.000001 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.050339 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.070827 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.419915 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker 54633 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 5368 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 354592 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 139013 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 116525 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 6709 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 686591 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 224265 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1587696 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 603288 # number of Writeback hits
-system.l2c.Writeback_hits::total 603288 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 917 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 938 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1855 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 350 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 564 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 36690 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 64535 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 101225 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 54633 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 5368 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 354592 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 175703 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 116525 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 6709 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 686591 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 288800 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1688921 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 54633 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 5368 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 354592 # number of overall hits
-system.l2c.overall_hits::cpu0.data 175703 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 116525 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 6709 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 686591 # number of overall hits
-system.l2c.overall_hits::cpu1.data 288800 # number of overall hits
-system.l2c.overall_hits::total 1688921 # number of overall hits
+system.l2c.occ_blocks::writebacks 15182.704930 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker 18.055930 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker 0.023183 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 2139.633455 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 1078.266225 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker 23.228189 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.itb.walker 0.012320 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 4084.926228 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 5046.245146 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.231670 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.dtb.walker 0.000276 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.032648 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.016453 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.dtb.walker 0.000354 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.062331 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.077000 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.420732 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker 49525 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 7421 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 332040 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 132891 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker 112998 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker 7553 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 699861 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 231630 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1573919 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 605876 # number of Writeback hits
+system.l2c.Writeback_hits::total 605876 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 897 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 1121 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 2018 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 196 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data 382 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 578 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 35379 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 65973 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 101352 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 49525 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 7421 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 332040 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 168270 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 112998 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 7553 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 699861 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 297603 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1675271 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 49525 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 7421 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 332040 # number of overall hits
+system.l2c.overall_hits::cpu0.data 168270 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 112998 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 7553 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 699861 # number of overall hits
+system.l2c.overall_hits::cpu1.data 297603 # number of overall hits
+system.l2c.overall_hits::total 1675271 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 81 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 9406 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 9212 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker 53 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker 7 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 8899 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 12145 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 39808 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 5322 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 5511 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 10833 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 766 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 527 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1293 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 66272 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 81260 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 147532 # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu0.inst 8347 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 8839 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker 55 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 10114 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 12836 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 40278 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 5127 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 5687 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 10814 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data 762 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data 599 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 1361 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 65841 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 81581 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 147422 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 81 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 9406 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 75484 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker 53 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker 7 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 8899 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 93405 # number of demand (read+write) misses
-system.l2c.demand_misses::total 187340 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 8347 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 74680 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker 55 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 10114 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 94417 # number of demand (read+write) misses
+system.l2c.demand_misses::total 187700 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 81 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 9406 # number of overall misses
-system.l2c.overall_misses::cpu0.data 75484 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 53 # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker 7 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 8899 # number of overall misses
-system.l2c.overall_misses::cpu1.data 93405 # number of overall misses
-system.l2c.overall_misses::total 187340 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 4223500 # number of ReadReq miss cycles
+system.l2c.overall_misses::cpu0.inst 8347 # number of overall misses
+system.l2c.overall_misses::cpu0.data 74680 # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker 55 # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 10114 # number of overall misses
+system.l2c.overall_misses::cpu1.data 94417 # number of overall misses
+system.l2c.overall_misses::total 187700 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 4226000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 261000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst 491867500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 480714000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 2767000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker 364500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 465541000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 634495500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 2080234000 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 18082000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 37415000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 55497000 # number of UpgradeReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst 436472500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 461376000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 2870500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 529146500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 670533000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 2104937500 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data 17145500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 38360500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 55506000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1985000 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5173000 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 7158000 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 3474814999 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 4268858500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 7743673499 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker 4223500 # number of demand (read+write) miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5435500 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total 7420500 # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 3452457999 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 4285420500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 7737878499 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker 4226000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 261000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 491867500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 3955528999 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker 2767000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker 364500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 465541000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 4903354000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 9823907499 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker 4223500 # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 436472500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 3913833999 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker 2870500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker 52000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 529146500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 4955953500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 9842815999 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker 4226000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 261000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 491867500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 3955528999 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker 2767000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker 364500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 465541000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 4903354000 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 9823907499 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 54714 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 5373 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 363998 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 148225 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 116578 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 6716 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 695490 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 236410 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1627504 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 603288 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 603288 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 6239 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 6449 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 12688 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 980 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 877 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 1857 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 102962 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 145795 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 248757 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 54714 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 5373 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 363998 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 251187 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 116578 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 6716 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 695490 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 382205 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1876261 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 54714 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 5373 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 363998 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 251187 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 116578 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 6716 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 695490 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 382205 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1876261 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001480 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000931 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.025841 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.062149 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000455 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.001042 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.012795 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.051373 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.853021 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.854551 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.781633 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.600912 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.643655 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.557358 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001480 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.000931 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.025841 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.300509 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000455 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker 0.001042 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.012795 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.244385 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001480 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.000931 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.025841 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.300509 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000455 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker 0.001042 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.012795 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.244385 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52141.975309 # average ReadReq miss latency
+system.l2c.overall_miss_latency::cpu0.inst 436472500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 3913833999 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker 2870500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker 52000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 529146500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 4955953500 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 9842815999 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 49606 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 7426 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 340387 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 141730 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 113053 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 7554 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 709975 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 244466 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1614197 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 605876 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 605876 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 6024 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 6808 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 12832 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data 958 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 981 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 1939 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 101220 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 147554 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 248774 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 49606 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 7426 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 340387 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 242950 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 113053 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 7554 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 709975 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 392020 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1862971 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 49606 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 7426 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 340387 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 242950 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 113053 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 7554 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 709975 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 392020 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1862971 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001633 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000673 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.024522 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.062365 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000486 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000132 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.014246 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.052506 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.851096 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.835341 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.795407 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.610601 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.650474 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.552889 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001633 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.000673 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.024522 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.307388 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000486 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker 0.000132 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.014246 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.240847 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001633 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.000673 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.024522 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.307388 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000486 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker 0.000132 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.014246 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.240847 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52172.839506 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52200 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52292.951308 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52183.456361 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52207.547170 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52071.428571 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52313.855489 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 52243.351173 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3397.594889 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6789.148975 # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2591.383812 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9815.939279 # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52432.626132 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52533.331282 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52141.975309 # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52290.942854 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52197.759928 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52190.909091 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52318.222266 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 52238.469928 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3344.158377 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6745.296290 # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2604.986877 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9074.290484 # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52436.293480 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52529.639254 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52172.839506 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52292.951308 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52402.217675 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52207.547170 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52071.428571 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 52313.855489 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 52495.626572 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52141.975309 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52290.942854 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52408.061047 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52190.909091 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 52318.222266 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 52490.054757 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52172.839506 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52292.951308 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52402.217675 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52207.547170 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52071.428571 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 52313.855489 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 52495.626572 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52290.942854 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52408.061047 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52190.909091 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 52318.222266 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 52490.054757 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 112128 # number of writebacks
-system.l2c.writebacks::total 112128 # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data 51 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst 13 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data 32 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data 51 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst 13 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data 32 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 98 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data 51 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst 13 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data 32 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 98 # number of overall MSHR hits
+system.l2c.writebacks::writebacks 111616 # number of writebacks
+system.l2c.writebacks::total 111616 # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.data 42 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.data 35 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data 42 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data 35 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data 42 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data 35 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total 91 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 81 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst 9404 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data 9161 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 53 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 7 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst 8886 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 12113 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 39710 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data 5322 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 5511 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 10833 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 766 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 527 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 1293 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data 66272 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 81260 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 147532 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst 8343 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data 8797 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 55 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 10104 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 12801 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 40187 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data 5127 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 5687 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 10814 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 762 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 599 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total 1361 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data 65841 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 81581 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 147422 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 81 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 9404 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 75433 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker 53 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker 7 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 8886 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 93373 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 187242 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst 8343 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data 74638 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker 55 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 10104 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 94382 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 187609 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 81 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 9404 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 75433 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker 53 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker 7 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 8886 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 93373 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 187242 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3242500 # number of ReadReq MSHR miss cycles
+system.l2c.overall_mshr_misses::cpu0.inst 8343 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data 74638 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker 55 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 10104 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 94382 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 187609 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3244000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 201000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 376846000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data 366960000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 2126500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 280000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 356559500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 485221000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 1591436500 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 213132000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 220571000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 433703000 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 30672000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 21105000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 51777000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2653014999 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3258420500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 5911435499 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3242500 # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 334368500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 352448500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 2202500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 40000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 405321000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 512811000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 1610636500 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 205370000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 227611500 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 432981500 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 30499500 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23997000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 54496500 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2635763499 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3271199500 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 5906962999 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3244000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 201000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 376846000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 3019974999 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2126500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 280000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 356559500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 3743641500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 7502871999 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3242500 # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 334368500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 2988211999 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2202500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 40000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 405321000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 3784010500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 7517599499 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3244000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 201000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 376846000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 3019974999 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2126500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 280000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 356559500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 3743641500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 7502871999 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5748500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 8468888000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 334368500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 2988211999 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2202500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 40000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 405321000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 3784010500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 7517599499 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5668500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 8247511500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1931000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123493861000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131970428500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 744865480 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31777562693 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 32522428173 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5748500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9213753480 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123718931000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131974042000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 707206480 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31817900108 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 32525106588 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5668500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8954717980 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1931000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155271423693 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 164492856673 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001480 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000931 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.025835 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.061805 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.001042 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012777 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.051237 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.853021 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.854551 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.781633 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.600912 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.643655 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.557358 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001480 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000931 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.025835 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.300306 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.001042 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012777 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.244301 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001480 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000931 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.025835 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.300306 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.001042 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012777 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.244301 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40030.864198 # average ReadReq mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155536831108 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 164499148588 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001633 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000673 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.024510 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.062069 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000486 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014231 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.052363 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.851096 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835341 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.795407 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.610601 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.650474 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.552889 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001633 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000673 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.024510 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.307215 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000486 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014231 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.240758 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001633 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000673 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.024510 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.307215 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000486 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014231 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.240758 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40049.382716 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40072.947682 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40056.762362 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40122.641509 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40077.729833 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40064.624304 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40045.454545 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40125.984695 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40057.871708 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.350620 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40023.770641 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.775457 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40047.438330 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.215702 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40098.701698 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40030.864198 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40114.904988 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40060.229670 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40056.563292 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40023.122912 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40025.590551 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40061.769616 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.251925 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40097.565610 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40049.382716 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40072.947682 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40035.196784 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40122.641509 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40077.729833 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40036.067405 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40045.454545 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40125.984695 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40093.404946 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40030.864198 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40114.904988 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40092.501748 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40049.382716 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40072.947682 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40035.196784 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40122.641509 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40077.729833 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40036.067405 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40045.454545 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40125.984695 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40093.404946 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40114.904988 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40092.501748 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7779192 # DTB read hits
-system.cpu0.dtb.read_misses 37115 # DTB read misses
-system.cpu0.dtb.write_hits 4594295 # DTB write hits
-system.cpu0.dtb.write_misses 6419 # DTB write misses
+system.cpu0.dtb.read_hits 7527759 # DTB read hits
+system.cpu0.dtb.read_misses 31435 # DTB read misses
+system.cpu0.dtb.write_hits 4435696 # DTB write hits
+system.cpu0.dtb.write_misses 6033 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 2014 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 4597 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 2072 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 4328 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 228 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 800 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7816307 # DTB read accesses
-system.cpu0.dtb.write_accesses 4600714 # DTB write accesses
+system.cpu0.dtb.perms_faults 803 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 7559194 # DTB read accesses
+system.cpu0.dtb.write_accesses 4441729 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 12373487 # DTB hits
-system.cpu0.dtb.misses 43534 # DTB misses
-system.cpu0.dtb.accesses 12417021 # DTB accesses
-system.cpu0.itb.inst_hits 4018220 # ITB inst hits
-system.cpu0.itb.inst_misses 4575 # ITB inst misses
+system.cpu0.dtb.hits 11963455 # DTB hits
+system.cpu0.dtb.misses 37468 # DTB misses
+system.cpu0.dtb.accesses 12000923 # DTB accesses
+system.cpu0.itb.inst_hits 3809486 # ITB inst hits
+system.cpu0.itb.inst_misses 6280 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1374 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1380 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1835 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1824 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 4022795 # ITB inst accesses
-system.cpu0.itb.hits 4018220 # DTB hits
-system.cpu0.itb.misses 4575 # DTB misses
-system.cpu0.itb.accesses 4022795 # DTB accesses
-system.cpu0.numCycles 58073431 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 3815766 # ITB inst accesses
+system.cpu0.itb.hits 3809486 # DTB hits
+system.cpu0.itb.misses 6280 # DTB misses
+system.cpu0.itb.accesses 3815766 # DTB accesses
+system.cpu0.numCycles 55441069 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 5437293 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 4256353 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 316271 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 3600228 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 2674120 # Number of BTB hits
+system.cpu0.BPredUnit.lookups 5212892 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 3951494 # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect 295394 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups 3415998 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 2549557 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 485080 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 65250 # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles 11048158 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 28487074 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 5437293 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 3159200 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 6739880 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1438397 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 59633 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 18694595 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 6724 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 30266 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 80153 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 218 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 4016097 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 175657 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 3180 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 37672027 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.986348 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.372863 # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS 460779 # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect 62243 # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles 10453565 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 27421447 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 5212892 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 3010336 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 6440117 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1388454 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 65669 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 17512846 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 6544 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 31892 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 74131 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 3807333 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 161414 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 4002 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 35574590 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.004938 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.398361 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 30938102 82.12% 82.12% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 539295 1.43% 83.56% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 754456 2.00% 85.56% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 605374 1.61% 87.17% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 572205 1.52% 88.68% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 499727 1.33% 90.01% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 619840 1.65% 91.66% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 357335 0.95% 92.61% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 2785693 7.39% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 29140690 81.91% 81.91% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 530074 1.49% 83.40% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 686036 1.93% 85.33% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 575113 1.62% 86.95% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 516761 1.45% 88.40% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 484002 1.36% 89.76% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 574923 1.62% 91.38% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 349762 0.98% 92.36% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 2717229 7.64% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 37672027 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.093628 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.490535 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 11376766 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 18792478 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 6048489 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 500890 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 953404 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 867804 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 60437 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 35787038 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 193524 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 953404 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 11914000 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 4629145 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 12457249 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 6001220 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 1717009 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 34527596 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 766 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 354930 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 888723 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 49 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 34587688 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 157020073 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 156979210 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 40863 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 26885692 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 7701996 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 453005 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 414730 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 4495926 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 6704710 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5162827 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 858153 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 869893 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 32576471 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 727676 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 32778157 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 81649 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 5740307 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 13396786 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 126207 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 37672027 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.870093 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.506550 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 35574590 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.094026 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.494605 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 10814757 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 17563508 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 5782354 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 479006 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 934965 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 835529 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 55823 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 34470555 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 179479 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 934965 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 11326555 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 4595002 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 11316835 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 5729017 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 1672216 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 33303546 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 955 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 363738 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 882856 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 34 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 33389165 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 151283000 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 151242578 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 40422 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 25698465 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 7690700 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 390539 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 354252 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 4298434 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 6455423 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 4976732 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 849969 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 853540 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 31433505 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 659467 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 31580110 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 81056 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 5706071 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 12925708 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 117932 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 35574590 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.887715 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.519071 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 24340985 64.61% 64.61% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 5232872 13.89% 78.50% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 2696429 7.16% 85.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2005933 5.32% 90.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1857666 4.93% 95.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 789251 2.10% 98.01% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 535159 1.42% 99.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 163101 0.43% 99.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 50631 0.13% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 22796169 64.08% 64.08% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 4955890 13.93% 78.01% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 2593205 7.29% 85.30% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 1941493 5.46% 90.76% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1799462 5.06% 95.82% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 771833 2.17% 97.99% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 508602 1.43% 99.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 158782 0.45% 99.86% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 49154 0.14% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 37672027 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 35574590 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 17215 1.80% 1.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 476 0.05% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 744103 77.93% 79.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 193089 20.22% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 35384 3.74% 3.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 453 0.05% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 728574 76.99% 80.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 181906 19.22% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 14281 0.04% 0.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 19588840 59.76% 59.81% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 43482 0.13% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 8 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 1004 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.94% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 8219170 25.08% 85.02% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 4911355 14.98% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 14281 0.05% 0.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 18843805 59.67% 59.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 42255 0.13% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 7 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 650 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 7938571 25.14% 84.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 4740521 15.01% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 32778157 # Type of FU issued
-system.cpu0.iq.rate 0.564426 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 954883 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.029132 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 104296789 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 39048181 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 30070598 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 10781 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 5570 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 4438 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 33712886 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 5873 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 258573 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 31580110 # Type of FU issued
+system.cpu0.iq.rate 0.569616 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 946317 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.029966 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 99788129 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 37802639 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 28957807 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 10678 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 5536 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 4399 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 32506335 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 5811 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 253441 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1274599 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 3983 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 9698 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 554608 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1254358 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3684 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 9621 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 525059 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 1948828 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 5242 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 1901492 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 5043 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 953404 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 3530697 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 77233 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 33359153 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 131395 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 6704710 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5162827 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 457179 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 36756 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 4503 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 9698 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 188494 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 122646 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 311140 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 32365577 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 8053232 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 412580 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 934965 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 3498549 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 78984 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 32152208 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 119958 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 6455423 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 4976732 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 398786 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 38665 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 4398 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 9621 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 177464 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 119524 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 296988 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 31195619 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 7789216 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 384491 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 55006 # number of nop insts executed
-system.cpu0.iew.exec_refs 12911062 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 4264405 # Number of branches executed
-system.cpu0.iew.exec_stores 4857830 # Number of stores executed
-system.cpu0.iew.exec_rate 0.557322 # Inst execution rate
-system.cpu0.iew.wb_sent 32156724 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 30075036 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 16051487 # num instructions producing a value
-system.cpu0.iew.wb_consumers 31416706 # num instructions consuming a value
+system.cpu0.iew.exec_nop 59236 # number of nop insts executed
+system.cpu0.iew.exec_refs 12477007 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 4073990 # Number of branches executed
+system.cpu0.iew.exec_stores 4687791 # Number of stores executed
+system.cpu0.iew.exec_rate 0.562681 # Inst execution rate
+system.cpu0.iew.wb_sent 30989414 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 28962206 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 15536163 # num instructions producing a value
+system.cpu0.iew.wb_consumers 30480637 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.517879 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.510922 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.522396 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.509706 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitCommittedInsts 20629701 # The number of committed instructions
-system.cpu0.commit.commitCommittedOps 27347563 # The number of committed instructions
-system.cpu0.commit.commitSquashedInsts 5860569 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 601469 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 274713 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 36749403 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.744163 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.705264 # Number of insts commited each cycle
+system.cpu0.commit.commitCommittedInsts 19711221 # The number of committed instructions
+system.cpu0.commit.commitCommittedOps 26183930 # The number of committed instructions
+system.cpu0.commit.commitSquashedInsts 5818378 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 541535 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 256688 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 34668404 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.755268 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.722296 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 26406070 71.85% 71.85% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 5210331 14.18% 86.03% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1671532 4.55% 90.58% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 813872 2.21% 92.80% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 646917 1.76% 94.56% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 387096 1.05% 95.61% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 442946 1.21% 96.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 193384 0.53% 97.34% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 977255 2.66% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 24842291 71.66% 71.66% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 4903680 14.14% 85.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1598724 4.61% 90.41% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 790644 2.28% 92.69% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 613460 1.77% 94.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 370313 1.07% 95.53% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 401864 1.16% 96.69% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 185143 0.53% 97.22% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 962285 2.78% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 36749403 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 20629701 # Number of instructions committed
-system.cpu0.commit.committedOps 27347563 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 34668404 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 19711221 # Number of instructions committed
+system.cpu0.commit.committedOps 26183930 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 10038330 # Number of memory references committed
-system.cpu0.commit.loads 5430111 # Number of loads committed
-system.cpu0.commit.membars 201113 # Number of memory barriers committed
-system.cpu0.commit.branches 3777893 # Number of branches committed
+system.cpu0.commit.refs 9652738 # Number of memory references committed
+system.cpu0.commit.loads 5201065 # Number of loads committed
+system.cpu0.commit.membars 194494 # Number of memory barriers committed
+system.cpu0.commit.branches 3582933 # Number of branches committed
system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 24270810 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 441070 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 977255 # number cycles where commit BW limit reached
+system.cpu0.commit.int_insts 23269679 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 421897 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 962285 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 68333926 # The number of ROB reads
-system.cpu0.rob.rob_writes 67371686 # The number of ROB writes
-system.cpu0.timesIdled 379272 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 20401404 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 5085475083 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 20605147 # Number of Instructions Simulated
-system.cpu0.committedOps 27323009 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 20605147 # Number of Instructions Simulated
-system.cpu0.cpi 2.818394 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.818394 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.354812 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.354812 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 150871425 # number of integer regfile reads
-system.cpu0.int_regfile_writes 29495246 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 4612 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 442 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 40364553 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 457015 # number of misc regfile writes
-system.cpu0.icache.replacements 364779 # number of replacements
-system.cpu0.icache.tagsinuse 511.052726 # Cycle average of tags in use
-system.cpu0.icache.total_refs 3619396 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 365291 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 9.908254 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 6333280000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 511.052726 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.998150 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.998150 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 3619396 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 3619396 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 3619396 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 3619396 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 3619396 # number of overall hits
-system.cpu0.icache.overall_hits::total 3619396 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 396554 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 396554 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 396554 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 396554 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 396554 # number of overall misses
-system.cpu0.icache.overall_misses::total 396554 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6048062987 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 6048062987 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 6048062987 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 6048062987 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 6048062987 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 6048062987 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 4015950 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 4015950 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 4015950 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 4015950 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 4015950 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 4015950 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.098745 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.098745 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.098745 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15251.549567 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15251.549567 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15251.549567 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 1568990 # number of cycles access was blocked
+system.cpu0.rob.rob_reads 65094034 # The number of ROB reads
+system.cpu0.rob.rob_writes 64941259 # The number of ROB writes
+system.cpu0.timesIdled 360737 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 19866479 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 5085563503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 19686667 # Number of Instructions Simulated
+system.cpu0.committedOps 26159376 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 19686667 # Number of Instructions Simulated
+system.cpu0.cpi 2.816173 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.816173 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.355092 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.355092 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 145393582 # number of integer regfile reads
+system.cpu0.int_regfile_writes 28417758 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 4580 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 450 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 38939704 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 443716 # number of misc regfile writes
+system.cpu0.icache.replacements 341473 # number of replacements
+system.cpu0.icache.tagsinuse 511.631456 # Cycle average of tags in use
+system.cpu0.icache.total_refs 3435816 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 341985 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 10.046686 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 6333594000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 511.631456 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.999280 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.999280 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 3435816 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 3435816 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 3435816 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 3435816 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 3435816 # number of overall hits
+system.cpu0.icache.overall_hits::total 3435816 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 371369 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 371369 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 371369 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 371369 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 371369 # number of overall misses
+system.cpu0.icache.overall_misses::total 371369 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5641865987 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 5641865987 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 5641865987 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 5641865987 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 5641865987 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 5641865987 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 3807185 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 3807185 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 3807185 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 3807185 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 3807185 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 3807185 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097544 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097544 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097544 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15192.075771 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15192.075771 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15192.075771 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 1691991 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 211 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 206 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 7435.971564 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 8213.548544 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks 18696 # number of writebacks
-system.cpu0.icache.writebacks::total 18696 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31138 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 31138 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 31138 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 31138 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 31138 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 31138 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 365416 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 365416 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 365416 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 365416 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 365416 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 365416 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4532086990 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 4532086990 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4532086990 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 4532086990 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4532086990 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 4532086990 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7723000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7723000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7723000 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total 7723000 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090991 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090991 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090991 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12402.541186 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12402.541186 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12402.541186 # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks 19233 # number of writebacks
+system.cpu0.icache.writebacks::total 19233 # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 29370 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 29370 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 29370 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 29370 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 29370 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 29370 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 341999 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 341999 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 341999 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 341999 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 341999 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 341999 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4224982491 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 4224982491 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4224982491 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 4224982491 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4224982491 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 4224982491 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7615500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7615500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7615500 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total 7615500 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.089830 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.089830 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.089830 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12353.786096 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12353.786096 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12353.786096 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 240620 # number of replacements
-system.cpu0.dcache.tagsinuse 465.804609 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 8050384 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 241002 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 33.403806 # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 49733000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 465.804609 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.909775 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total 0.909775 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 4986735 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 4986735 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 2710782 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 2710782 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 158772 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 158772 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 156309 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 156309 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 7697517 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 7697517 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 7697517 # number of overall hits
-system.cpu0.dcache.overall_hits::total 7697517 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 337926 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 337926 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1466374 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1466374 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8662 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 8662 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7736 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 7736 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1804300 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1804300 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1804300 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1804300 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4785519500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 4785519500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60142300903 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 60142300903 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99268000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 99268000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 83415000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 83415000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 64927820403 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 64927820403 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 64927820403 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 64927820403 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 5324661 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 5324661 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 4177156 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 4177156 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 167434 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 167434 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 164045 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 164045 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 9501817 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 9501817 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 9501817 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 9501817 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063464 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.351046 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051734 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047158 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.189890 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.189890 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14161.442150 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41014.298469 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11460.170861 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10782.704240 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35985.047056 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35985.047056 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 4268990 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 2272500 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 373 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 104 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11445.013405 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 21850.961538 # average number of cycles each access was blocked
+system.cpu0.dcache.replacements 231957 # number of replacements
+system.cpu0.dcache.tagsinuse 430.483417 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 7734943 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 232325 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 33.293632 # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 49672000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data 430.483417 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.840788 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.840788 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data 4799900 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 4799900 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 2590245 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 2590245 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 154697 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 154697 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152346 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 152346 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 7390145 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 7390145 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 7390145 # number of overall hits
+system.cpu0.dcache.overall_hits::total 7390145 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 331500 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 331500 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1445399 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1445399 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8824 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 8824 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7928 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 7928 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 1776899 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 1776899 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 1776899 # number of overall misses
+system.cpu0.dcache.overall_misses::total 1776899 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4661132500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 4661132500 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 59622143898 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 59622143898 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99172000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 99172000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 83748000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 83748000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 64283276398 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 64283276398 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 64283276398 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 64283276398 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 5131400 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 5131400 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 4035644 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 4035644 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163521 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 163521 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160274 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 160274 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 9167044 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 9167044 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 9167044 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 9167044 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064602 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.358158 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053962 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049465 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.193836 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.193836 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14060.731523 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41249.609207 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11238.893926 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10563.572149 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36177.225829 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36177.225829 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 3382986 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 2017500 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 334 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 95 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10128.700599 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 21236.842105 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 213485 # number of writebacks
-system.cpu0.dcache.writebacks::total 213485 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 174573 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 174573 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1346571 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1346571 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 614 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 614 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1521144 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 1521144 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1521144 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 1521144 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 163353 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 163353 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119803 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 119803 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8048 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8048 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7735 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7735 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 283156 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 283156 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 283156 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 283156 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2116822500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2116822500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4307053989 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4307053989 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66689500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66689500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 60159000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 60159000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6423876489 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 6423876489 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6423876489 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 6423876489 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9482121000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9482121000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 884869891 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 884869891 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10366990891 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10366990891 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030679 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028681 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048067 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047152 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029800 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029800 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12958.577437 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35951.136357 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8286.468688 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7777.504848 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22686.704463 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22686.704463 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 207854 # number of writebacks
+system.cpu0.dcache.writebacks::total 207854 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 173784 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 173784 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1326908 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 1326908 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 637 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 637 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 1500692 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 1500692 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 1500692 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 1500692 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 157716 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 157716 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 118491 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 118491 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8187 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8187 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7924 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 7924 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 276207 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 276207 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 276207 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 276207 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2028922000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2028922000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4262146485 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4262146485 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66363000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66363000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 59926500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 59926500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6291068485 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 6291068485 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6291068485 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 6291068485 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9234849500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9234849500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 843734891 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 843734891 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10078584391 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10078584391 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030735 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029361 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.050067 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049440 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030130 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030130 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12864.401836 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35970.212801 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8105.899597 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7562.657749 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22776.643912 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22776.643912 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 44907962 # DTB read hits
-system.cpu1.dtb.read_misses 73330 # DTB read misses
-system.cpu1.dtb.write_hits 7780018 # DTB write hits
-system.cpu1.dtb.write_misses 20100 # DTB write misses
+system.cpu1.dtb.read_hits 45296976 # DTB read hits
+system.cpu1.dtb.read_misses 68040 # DTB read misses
+system.cpu1.dtb.write_hits 7958541 # DTB write hits
+system.cpu1.dtb.write_misses 20787 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2652 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 7203 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 561 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2725 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 7868 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 603 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 1824 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 44981292 # DTB read accesses
-system.cpu1.dtb.write_accesses 7800118 # DTB write accesses
+system.cpu1.dtb.perms_faults 1726 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 45365016 # DTB read accesses
+system.cpu1.dtb.write_accesses 7979328 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 52687980 # DTB hits
-system.cpu1.dtb.misses 93430 # DTB misses
-system.cpu1.dtb.accesses 52781410 # DTB accesses
-system.cpu1.itb.inst_hits 10156376 # ITB inst hits
-system.cpu1.itb.inst_misses 7457 # ITB inst misses
+system.cpu1.dtb.hits 53255517 # DTB hits
+system.cpu1.dtb.misses 88827 # DTB misses
+system.cpu1.dtb.accesses 53344344 # DTB accesses
+system.cpu1.itb.inst_hits 10421118 # ITB inst hits
+system.cpu1.itb.inst_misses 7923 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1545 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1559 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 5007 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 4993 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 10163833 # ITB inst accesses
-system.cpu1.itb.hits 10156376 # DTB hits
-system.cpu1.itb.misses 7457 # DTB misses
-system.cpu1.itb.accesses 10163833 # DTB accesses
-system.cpu1.numCycles 361463197 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 10429041 # ITB inst accesses
+system.cpu1.itb.hits 10421118 # DTB hits
+system.cpu1.itb.misses 7923 # DTB misses
+system.cpu1.itb.accesses 10429041 # DTB accesses
+system.cpu1.numCycles 361284565 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 10782508 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 8772381 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 635923 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 7402063 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 5909244 # Number of BTB hits
+system.cpu1.BPredUnit.lookups 11160075 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 8957573 # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect 655963 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups 7602711 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 6100291 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 873700 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 139717 # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles 23605299 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 77286787 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 10782508 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 6782944 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 16557542 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 5336622 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 96051 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 76350866 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 5280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 106359 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 159348 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 263 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 10151102 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 836280 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 4015 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 120517405 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.782275 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.157111 # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS 909624 # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect 143125 # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles 24152579 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 79243321 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 11160075 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 7009915 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 17005367 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 5503080 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 106407 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 74478012 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 5575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 116210 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 165404 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 287 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 10415863 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 850791 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 4371 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 119805091 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.807068 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.185605 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 103969658 86.27% 86.27% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 987113 0.82% 87.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 1198247 0.99% 88.08% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 2181121 1.81% 89.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1404675 1.17% 91.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 731318 0.61% 91.66% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 2384511 1.98% 93.64% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 517678 0.43% 94.07% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 7143084 5.93% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 102809911 85.81% 85.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 1026487 0.86% 86.67% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 1244623 1.04% 87.71% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 2220450 1.85% 89.56% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1447523 1.21% 90.77% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 762352 0.64% 91.41% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 2446430 2.04% 93.45% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 545220 0.46% 93.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 7302095 6.09% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 120517405 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.029830 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.213816 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 25233877 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 76283550 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 14821072 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 657863 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 3521043 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1494975 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 117774 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 87693964 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 382895 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 3521043 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 26831414 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 32478721 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 39236731 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 13889721 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 4559775 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 81167341 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 2581 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 635823 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 3200516 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 46226 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 85740662 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 375398775 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 375349065 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 49710 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 53651640 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 32089021 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 776045 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 700116 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 8935980 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 15610664 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 9406979 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 1201620 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1579608 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 72666150 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1193677 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 96590201 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 142158 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 20735703 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 58926609 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 234264 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 120517405 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.801463 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.526860 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 119805091 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.030890 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.219338 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 25854345 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 74385490 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 15310008 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 600331 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 3654917 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1553748 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 123029 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 89962683 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 400925 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 3654917 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 27463225 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 32802291 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 37038310 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 14280523 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 4565825 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 83469542 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 3103 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 679234 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 3297923 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 45820 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 88189114 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 385593776 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 385544391 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 49385 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 54868386 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 33320727 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 602216 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 524905 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 8650801 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 16023709 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 9632090 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 1276299 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1729146 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 74907136 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1031599 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 98321113 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 155877 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 21592981 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 61005208 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 224170 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 119805091 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.820676 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.545860 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 86833748 72.05% 72.05% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 9975019 8.28% 80.33% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 4940804 4.10% 84.43% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 4069487 3.38% 87.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 11024826 9.15% 96.95% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 2090694 1.73% 98.69% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1200483 1.00% 99.68% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 289311 0.24% 99.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 93033 0.08% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 85906342 71.71% 71.71% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 9617362 8.03% 79.73% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 5105765 4.26% 83.99% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 4221138 3.52% 87.52% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 11132119 9.29% 96.81% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 2139642 1.79% 98.60% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1275484 1.06% 99.66% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 308695 0.26% 99.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 98544 0.08% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 120517405 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 119805091 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 40307 0.50% 0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 997 0.01% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 7705811 95.37% 95.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 333073 4.12% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 44454 0.55% 0.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 993 0.01% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 7729676 95.36% 95.92% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 330610 4.08% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 92768 0.10% 0.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 42073039 43.56% 43.65% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 68661 0.07% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 25 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 44 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 2 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1453 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 46174618 47.80% 91.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 8179589 8.47% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 92819 0.09% 0.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 43197176 43.93% 44.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 69729 0.07% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 31 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 38 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 4 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1798 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 46580491 47.38% 91.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 8379023 8.52% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 96590201 # Type of FU issued
-system.cpu1.iq.rate 0.267220 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 8080188 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.083654 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 322001182 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 94611209 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 59943384 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 12160 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 6852 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 5542 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 104571300 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 6321 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 377653 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 98321113 # Type of FU issued
+system.cpu1.iq.rate 0.272143 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 8105733 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.082441 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 324785513 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 97548571 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 61562518 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 11987 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 6778 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 5521 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 106327792 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 6235 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 430499 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 4689619 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 6336 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 23311 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1773508 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 4865573 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 7656 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 24407 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1834498 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 32175805 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 1149678 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 32207869 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 1151172 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 3521043 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 25065136 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 359091 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 74029865 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 214492 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 15610664 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 9406979 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 810165 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 59786 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 8576 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 23311 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 385716 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 238696 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 624412 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 93721321 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 45339640 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 2868880 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 3654917 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 25274079 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 368524 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 76147540 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 230680 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 16023709 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 9632090 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 636792 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 64221 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 8659 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 24407 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 397735 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 243587 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 641322 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 95426692 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 45740593 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 2894421 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 170038 # number of nop insts executed
-system.cpu1.iew.exec_refs 53422835 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 7793526 # Number of branches executed
-system.cpu1.iew.exec_stores 8083195 # Number of stores executed
-system.cpu1.iew.exec_rate 0.259283 # Inst execution rate
-system.cpu1.iew.wb_sent 92395030 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 59948926 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 32815937 # num instructions producing a value
-system.cpu1.iew.wb_consumers 59243985 # num instructions consuming a value
+system.cpu1.iew.exec_nop 208805 # number of nop insts executed
+system.cpu1.iew.exec_refs 54014697 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 8051531 # Number of branches executed
+system.cpu1.iew.exec_stores 8274104 # Number of stores executed
+system.cpu1.iew.exec_rate 0.264132 # Inst execution rate
+system.cpu1.iew.wb_sent 94059839 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 61568039 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 33920997 # num instructions producing a value
+system.cpu1.iew.wb_consumers 61750617 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.165851 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.553912 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.170414 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.549322 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitCommittedInsts 41354162 # The number of committed instructions
-system.cpu1.commit.commitCommittedOps 52669090 # The number of committed instructions
-system.cpu1.commit.commitSquashedInsts 21302262 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 959413 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 549125 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 117050265 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.449970 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.406060 # Number of insts commited each cycle
+system.cpu1.commit.commitCommittedInsts 42291661 # The number of committed instructions
+system.cpu1.commit.commitCommittedOps 53866202 # The number of committed instructions
+system.cpu1.commit.commitSquashedInsts 22216320 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 807429 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 565831 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 116206088 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.463540 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.434749 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 97973751 83.70% 83.70% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 9696174 8.28% 91.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 2557084 2.18% 94.17% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1440070 1.23% 95.40% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1185226 1.01% 96.41% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 698819 0.60% 97.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 1094067 0.93% 97.95% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 501455 0.43% 98.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1903619 1.63% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 97183761 83.63% 83.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 9338835 8.04% 91.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 2558958 2.20% 93.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1577703 1.36% 95.23% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1195507 1.03% 96.26% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 711645 0.61% 96.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 1133703 0.98% 97.84% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 513937 0.44% 98.29% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1992039 1.71% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 117050265 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 41354162 # Number of instructions committed
-system.cpu1.commit.committedOps 52669090 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 116206088 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 42291661 # Number of instructions committed
+system.cpu1.commit.committedOps 53866202 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 18554516 # Number of memory references committed
-system.cpu1.commit.loads 10921045 # Number of loads committed
-system.cpu1.commit.membars 235754 # Number of memory barriers committed
-system.cpu1.commit.branches 6572629 # Number of branches committed
+system.cpu1.commit.refs 18955728 # Number of memory references committed
+system.cpu1.commit.loads 11158136 # Number of loads committed
+system.cpu1.commit.membars 242500 # Number of memory barriers committed
+system.cpu1.commit.branches 6770430 # Number of branches committed
system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 46931412 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 612362 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1903619 # number cycles where commit BW limit reached
+system.cpu1.commit.int_insts 47963823 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 631876 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1992039 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 187930171 # The number of ROB reads
-system.cpu1.rob.rob_writes 151588010 # The number of ROB writes
-system.cpu1.timesIdled 1544590 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 240945792 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 4782780444 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 41228335 # Number of Instructions Simulated
-system.cpu1.committedOps 52543263 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 41228335 # Number of Instructions Simulated
-system.cpu1.cpi 8.767349 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 8.767349 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.114060 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.114060 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 421568276 # number of integer regfile reads
-system.cpu1.int_regfile_writes 62748878 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 4369 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 2038 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 99504542 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 498546 # number of misc regfile writes
-system.cpu1.icache.replacements 696735 # number of replacements
-system.cpu1.icache.tagsinuse 498.773379 # Cycle average of tags in use
-system.cpu1.icache.total_refs 9395224 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 697247 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 13.474743 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 74291126000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 498.773379 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.974167 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.974167 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 9395224 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 9395224 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 9395224 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 9395224 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 9395224 # number of overall hits
-system.cpu1.icache.overall_hits::total 9395224 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 755826 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 755826 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 755826 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 755826 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 755826 # number of overall misses
-system.cpu1.icache.overall_misses::total 755826 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11037584991 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 11037584991 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 11037584991 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 11037584991 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 11037584991 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 11037584991 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 10151050 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 10151050 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 10151050 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 10151050 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 10151050 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 10151050 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074458 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074458 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074458 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14603.341233 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14603.341233 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14603.341233 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 1489994 # number of cycles access was blocked
+system.cpu1.rob.rob_reads 189074073 # The number of ROB reads
+system.cpu1.rob.rob_writes 155943577 # The number of ROB writes
+system.cpu1.timesIdled 1562911 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 241479474 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 4780310719 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 42165834 # Number of Instructions Simulated
+system.cpu1.committedOps 53740375 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 42165834 # Number of Instructions Simulated
+system.cpu1.cpi 8.568183 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 8.568183 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.116711 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.116711 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 429426444 # number of integer regfile reads
+system.cpu1.int_regfile_writes 64384425 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 4325 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 2046 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 102104658 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 512737 # number of misc regfile writes
+system.cpu1.icache.replacements 711552 # number of replacements
+system.cpu1.icache.tagsinuse 498.766119 # Cycle average of tags in use
+system.cpu1.icache.total_refs 9643450 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 712064 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 13.542954 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 74281042000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst 498.766119 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.974153 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.974153 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 9643450 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 9643450 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 9643450 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 9643450 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 9643450 # number of overall hits
+system.cpu1.icache.overall_hits::total 9643450 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 772363 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 772363 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 772363 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 772363 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 772363 # number of overall misses
+system.cpu1.icache.overall_misses::total 772363 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11329505492 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 11329505492 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 11329505492 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 11329505492 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 11329505492 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 11329505492 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 10415813 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 10415813 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 10415813 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 10415813 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 10415813 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 10415813 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074153 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074153 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074153 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14668.627953 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14668.627953 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14668.627953 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 1533994 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 235 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 234 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs 6340.400000 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 6555.529915 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks 33229 # number of writebacks
-system.cpu1.icache.writebacks::total 33229 # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 58554 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 58554 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 58554 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 58554 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 58554 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 58554 # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 697272 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 697272 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 697272 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 697272 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 697272 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 697272 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8249763494 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 8249763494 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8249763494 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 8249763494 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8249763494 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 8249763494 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2572500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068690 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068690 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068690 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11831.485409 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11831.485409 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11831.485409 # average overall mshr miss latency
+system.cpu1.icache.writebacks::writebacks 32964 # number of writebacks
+system.cpu1.icache.writebacks::total 32964 # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 60264 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total 60264 # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst 60264 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total 60264 # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst 60264 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total 60264 # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 712099 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 712099 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 712099 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 712099 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 712099 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 712099 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8466389994 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 8466389994 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8466389994 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 8466389994 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8466389994 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 8466389994 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2573500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2573500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2573500 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total 2573500 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068367 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068367 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068367 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11889.344029 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11889.344029 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11889.344029 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 407382 # number of replacements
-system.cpu1.dcache.tagsinuse 452.475492 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 14784663 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 407894 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 36.246336 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 72560362000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 452.475492 # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data 0.883741 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total 0.883741 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 9748444 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 9748444 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 4751218 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 4751218 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 123467 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 123467 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 116541 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 116541 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 14499662 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 14499662 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 14499662 # number of overall hits
-system.cpu1.dcache.overall_hits::total 14499662 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 454636 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 454636 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 1699248 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 1699248 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14155 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 14155 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10110 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 10110 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 2153884 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 2153884 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 2153884 # number of overall misses
-system.cpu1.dcache.overall_misses::total 2153884 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6834637000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 6834637000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 56740092404 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 56740092404 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 170503000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 170503000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 85674000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 85674000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 63574729404 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 63574729404 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 63574729404 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 63574729404 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 10203080 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 10203080 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 6450466 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 6450466 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 137622 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 137622 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 126651 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 126651 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 16653546 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 16653546 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 16653546 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 16653546 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044559 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.263430 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102854 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.079826 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.129335 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.129335 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15033.206785 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33391.295681 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12045.425645 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8474.183976 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29516.320008 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29516.320008 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 14003056 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 5014500 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 3116 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 133 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4493.920411 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 37703.007519 # average number of cycles each access was blocked
+system.cpu1.dcache.replacements 416651 # number of replacements
+system.cpu1.dcache.tagsinuse 465.227268 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 15192855 # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs 417163 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 36.419469 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 72551040000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data 465.227268 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data 0.908647 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total 0.908647 # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data 10025124 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 10025124 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 4871876 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 4871876 # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 126729 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 126729 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 119900 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 119900 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 14897000 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 14897000 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 14897000 # number of overall hits
+system.cpu1.dcache.overall_hits::total 14897000 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 473956 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 473956 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 1726769 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 1726769 # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14662 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 14662 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10568 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 10568 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 2200725 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 2200725 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 2200725 # number of overall misses
+system.cpu1.dcache.overall_misses::total 2200725 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7150775500 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 7150775500 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 57296789383 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 57296789383 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 176168500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 176168500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 91818000 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 91818000 # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 64447564883 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 64447564883 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 64447564883 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 64447564883 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 10499080 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 10499080 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 6598645 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 6598645 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 141391 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 141391 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 130468 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 130468 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 17097725 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 17097725 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 17097725 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 17097725 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045143 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.261685 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.103698 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081001 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.128714 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.128714 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15087.424782 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33181.502206 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12015.311690 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8688.304315 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29284.697035 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29284.697035 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 15243046 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 5411000 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 3282 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 148 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4644.438147 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 36560.810811 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 337879 # number of writebacks
-system.cpu1.dcache.writebacks::total 337879 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 192117 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 192117 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1524857 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 1524857 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1136 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1136 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 1716974 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 1716974 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 1716974 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 1716974 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 262519 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 262519 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 174391 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 174391 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13019 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13019 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10105 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 10105 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 436910 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 436910 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 436910 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 436910 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3282878000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3282878000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5492297055 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5492297055 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 117597000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 117597000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55303500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 55303500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2501 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2501 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8775175055 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 8775175055 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8775175055 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 8775175055 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137933377000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137933377000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41618372048 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41618372048 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179551749048 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179551749048 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025729 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027035 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.094600 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.079786 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026235 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026235 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12505.296759 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31494.154257 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9032.721407 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5472.884711 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 345826 # number of writebacks
+system.cpu1.dcache.writebacks::total 345826 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 203766 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 203766 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1549585 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 1549585 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1246 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1246 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 1753351 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 1753351 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 1753351 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 1753351 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 270190 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 270190 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 177184 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 177184 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13416 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13416 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10560 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 10560 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 447374 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 447374 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 447374 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 447374 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3410102500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3410102500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5540518545 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5540518545 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 120430000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 120430000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60079000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60079000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8950621045 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 8950621045 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8950621045 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 8950621045 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 138186102000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 138186102000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41660941677 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41660941677 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179847043677 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179847043677 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025735 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026852 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.094886 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080939 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026166 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026166 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12621.127725 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31269.858142 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8976.595110 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5689.299242 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20084.628539 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20084.628539 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20007.021072 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20007.021072 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308183454966 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1308183454966 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308183454966 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1308183454966 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308112364906 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1308112364906 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308112364906 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1308112364906 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 38029 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 36030 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 59437 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 61524 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/dist/m5/system/binaries/boot.arm
+boot_loader=/projects/pd/randd/dist/binaries/boot.arm
boot_loader_mem=system.realview.nvmem
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
[system.cf0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-arm-ael.img
+image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu]
header_cycles=1
use_default_range=false
width=64
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
max_mem_size=268435456
mem_start_addr=0
system=system
pio=system.iobus.master[1]
-[system.realview.rtc_fake]
-type=AmbaFake
-amba_id=266289
-ignore_access=false
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+gic=system.realview.gic
+int_delay=100000
+int_num=42
pio_addr=268529664
pio_latency=1000
system=system
+time=Thu Jan 1 00:00:00 2009
pio=system.iobus.master[23]
[system.realview.sci_fake]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:45:32
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 18:11:20
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3
-The currently selected ARM platforms doesn't support
- the amount of DRAM you've selected. Please try
- another platform
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2503099557500 because m5_exit instruction encountered
+Exiting @ tick 2501676293500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.503100 # Number of seconds simulated
-sim_ticks 2503099557500 # Number of ticks simulated
-final_tick 2503099557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.501676 # Number of seconds simulated
+sim_ticks 2501676293500 # Number of ticks simulated
+final_tick 2501676293500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 80117 # Simulator instruction rate (inst/s)
-host_op_rate 103484 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3373282088 # Simulator tick rate (ticks/s)
-host_mem_usage 383952 # Number of bytes of host memory used
-host_seconds 742.04 # Real time elapsed on the host
-sim_insts 59449445 # Number of instructions simulated
-sim_ops 76789092 # Number of ops (including micro ops) simulated
+host_inst_rate 93944 # Simulator instruction rate (inst/s)
+host_op_rate 121345 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3953091411 # Simulator tick rate (ticks/s)
+host_mem_usage 381372 # Number of bytes of host memory used
+host_seconds 632.84 # Real time elapsed on the host
+sim_insts 59451291 # Number of instructions simulated
+sim_ops 76792341 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read 130740776 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 1120320 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 9586312 # Number of bytes written to this memory
-system.physmem.num_reads 15115704 # Number of read requests responded to by this memory
-system.physmem.num_writes 856678 # Number of write requests responded to by this memory
+system.physmem.bytes_read 129652968 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1121024 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 9585096 # Number of bytes written to this memory
+system.physmem.num_reads 14979455 # Number of read requests responded to by this memory
+system.physmem.num_writes 856659 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 52231553 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 447573 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 3829777 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 56061329 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 119794 # number of replacements
-system.l2c.tagsinuse 26073.611012 # Cycle average of tags in use
-system.l2c.total_refs 1840774 # Total number of references to valid blocks.
-system.l2c.sampled_refs 150725 # Sample count of references to valid blocks.
-system.l2c.avg_refs 12.212798 # Average number of references to valid blocks.
+system.physmem.bw_read 51826437 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 448109 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 3831469 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 55657906 # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 119784 # number of replacements
+system.l2c.tagsinuse 25999.615357 # Cycle average of tags in use
+system.l2c.total_refs 1826145 # Total number of references to valid blocks.
+system.l2c.sampled_refs 150763 # Sample count of references to valid blocks.
+system.l2c.avg_refs 12.112687 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 14308.761179 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker 64.610993 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker 0.928498 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst 6189.887268 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data 5509.423074 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.218334 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker 0.000986 # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks 14272.421964 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker 65.344146 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker 0.932012 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst 6169.201034 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data 5491.716201 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.217780 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker 0.000997 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker 0.000014 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst 0.094450 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data 0.084067 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.397852 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker 152848 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker 11656 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst 998872 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data 377319 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1540695 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 633173 # number of Writeback hits
-system.l2c.Writeback_hits::total 633173 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data 44 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 44 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu.data 5 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data 105891 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 105891 # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker 152848 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker 11656 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst 998872 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data 483210 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1646586 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker 152848 # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker 11656 # number of overall hits
-system.l2c.overall_hits::cpu.inst 998872 # number of overall hits
-system.l2c.overall_hits::cpu.data 483210 # number of overall hits
-system.l2c.overall_hits::total 1646586 # number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker 147 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.itb.walker 12 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst 17382 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data 19146 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 36687 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data 3313 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 3313 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data 140346 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 140346 # number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker 147 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.itb.walker 12 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst 17382 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data 159492 # number of demand (read+write) misses
-system.l2c.demand_misses::total 177033 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker 147 # number of overall misses
-system.l2c.overall_misses::cpu.itb.walker 12 # number of overall misses
-system.l2c.overall_misses::cpu.inst 17382 # number of overall misses
-system.l2c.overall_misses::cpu.data 159492 # number of overall misses
-system.l2c.overall_misses::total 177033 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker 7686500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.itb.walker 617000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst 910008500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data 1001033000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 1919345000 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data 1206000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 1206000 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data 7379766500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 7379766500 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker 7686500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.itb.walker 617000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst 910008500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data 8380799500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 9299111500 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker 7686500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.itb.walker 617000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst 910008500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data 8380799500 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 9299111500 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker 152995 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker 11668 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst 1016254 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data 396465 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1577382 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 633173 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 633173 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data 3357 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 3357 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data 246237 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 246237 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker 152995 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker 11668 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst 1016254 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data 642702 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1823619 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker 152995 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker 11668 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst 1016254 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data 642702 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1823619 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000961 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001028 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst 0.017104 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data 0.048292 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data 0.986893 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data 0.569963 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker 0.000961 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker 0.001028 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst 0.017104 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data 0.248159 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker 0.000961 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.itb.walker 0.001028 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst 0.017104 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data 0.248159 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52289.115646 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 51416.666667 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52353.497871 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52284.184686 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data 364.020525 # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52582.663560 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52289.115646 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.itb.walker 51416.666667 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 52353.497871 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52546.833070 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52289.115646 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.itb.walker 51416.666667 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 52353.497871 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52546.833070 # average overall miss latency
+system.l2c.occ_percent::cpu.inst 0.094135 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data 0.083797 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.396723 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker 141919 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker 12116 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst 995766 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data 377927 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1527728 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 634955 # number of Writeback hits
+system.l2c.Writeback_hits::total 634955 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data 46 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 46 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu.data 7 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data 105770 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 105770 # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker 141919 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker 12116 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst 995766 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data 483697 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1633498 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker 141919 # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker 12116 # number of overall hits
+system.l2c.overall_hits::cpu.inst 995766 # number of overall hits
+system.l2c.overall_hits::cpu.data 483697 # number of overall hits
+system.l2c.overall_hits::total 1633498 # number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker 157 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker 13 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst 17392 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data 19166 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 36728 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data 3302 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 3302 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data 140335 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 140335 # number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker 157 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker 13 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst 17392 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data 159501 # number of demand (read+write) misses
+system.l2c.demand_misses::total 177063 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker 157 # number of overall misses
+system.l2c.overall_misses::cpu.itb.walker 13 # number of overall misses
+system.l2c.overall_misses::cpu.inst 17392 # number of overall misses
+system.l2c.overall_misses::cpu.data 159501 # number of overall misses
+system.l2c.overall_misses::total 177063 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker 8196500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.itb.walker 677000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst 910933000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data 1001503500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 1921310000 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data 1203000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 1203000 # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data 7367598500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 7367598500 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker 8196500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.itb.walker 677000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst 910933000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data 8369102000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 9288908500 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker 8196500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.itb.walker 677000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.inst 910933000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data 8369102000 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 9288908500 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker 142076 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker 12129 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst 1013158 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data 397093 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1564456 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 634955 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 634955 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data 3348 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 3348 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu.data 10 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data 246105 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 246105 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker 142076 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker 12129 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst 1013158 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data 643198 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1810561 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker 142076 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker 12129 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst 1013158 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data 643198 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1810561 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001105 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001072 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst 0.017166 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data 0.048266 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data 0.986260 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.300000 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data 0.570224 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker 0.001105 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker 0.001072 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst 0.017166 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data 0.247981 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker 0.001105 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker 0.001072 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst 0.017166 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data 0.247981 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52207.006369 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52076.923077 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52376.552438 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52254.174058 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data 364.324652 # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52500.078384 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52207.006369 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.itb.walker 52076.923077 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52376.552438 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52470.529965 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52207.006369 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.itb.walker 52076.923077 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52376.552438 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52470.529965 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 102660 # number of writebacks
-system.l2c.writebacks::total 102660 # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu.itb.walker 1 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu.itb.walker 1 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu.data 79 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu.itb.walker 1 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu.data 79 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 93 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 147 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.itb.walker 11 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst 17369 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data 19067 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 36594 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data 3313 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 3313 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data 140346 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 140346 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.dtb.walker 147 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.itb.walker 11 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst 17369 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data 159413 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 176940 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.dtb.walker 147 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.itb.walker 11 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst 17369 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data 159413 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 176940 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 5904000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 442000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst 697218500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data 765075000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 1468639500 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 133817000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 133817000 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5636526500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 5636526500 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 5904000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.itb.walker 442000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst 697218500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data 6401601500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 7105166000 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 5904000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.itb.walker 442000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst 697218500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data 6401601500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 7105166000 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5507000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131763880500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131769387500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32348463263 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 32348463263 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5507000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data 164112343763 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 164117850763 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048093 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986893 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569963 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data 0.248036 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data 0.248036 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40141.545282 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40125.609692 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40391.488077 # average UpgradeReq mshr miss latency
+system.l2c.writebacks::writebacks 102641 # number of writebacks
+system.l2c.writebacks::total 102641 # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu.data 81 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu.data 81 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total 91 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 157 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.itb.walker 13 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst 17382 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data 19085 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 36637 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data 3302 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 3302 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data 140335 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 140335 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker 157 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.itb.walker 13 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst 17382 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data 159420 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 176972 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker 157 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.itb.walker 13 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst 17382 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data 159420 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 176972 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 6288500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 521000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst 698170500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data 765243500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 1470223500 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 132738500 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 132738500 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5623589000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 5623589000 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 6288500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.itb.walker 521000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst 698170500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data 6388832500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 7093812500 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 6288500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.itb.walker 521000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst 698170500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data 6388832500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 7093812500 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5427000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131765321500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131770748500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32346079731 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 32346079731 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5427000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data 164111401231 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 164116828231 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001105 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001072 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017156 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048062 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986260 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.300000 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.570224 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001105 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001072 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst 0.017156 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data 0.247855 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001105 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001072 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst 0.017156 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data 0.247855 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40076.923077 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40166.292717 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.594184 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40199.424591 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40161.646930 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40141.545282 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40157.336604 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40141.545282 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40157.336604 # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40072.604838 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40076.923077 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40166.292717 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.476728 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40076.923077 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40166.292717 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.476728 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51948606 # DTB read hits
-system.cpu.dtb.read_misses 101816 # DTB read misses
-system.cpu.dtb.write_hits 11910706 # DTB write hits
-system.cpu.dtb.write_misses 24423 # DTB write misses
+system.cpu.dtb.read_hits 52069399 # DTB read hits
+system.cpu.dtb.read_misses 92258 # DTB read misses
+system.cpu.dtb.write_hits 11926847 # DTB write hits
+system.cpu.dtb.write_misses 25023 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4440 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 5598 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 665 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 4540 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 5662 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 693 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 2849 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 52050422 # DTB read accesses
-system.cpu.dtb.write_accesses 11935129 # DTB write accesses
+system.cpu.dtb.perms_faults 2731 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 52161657 # DTB read accesses
+system.cpu.dtb.write_accesses 11951870 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63859312 # DTB hits
-system.cpu.dtb.misses 126239 # DTB misses
-system.cpu.dtb.accesses 63985551 # DTB accesses
-system.cpu.itb.inst_hits 13611127 # ITB inst hits
-system.cpu.itb.inst_misses 11794 # ITB inst misses
+system.cpu.dtb.hits 63996246 # DTB hits
+system.cpu.dtb.misses 117281 # DTB misses
+system.cpu.dtb.accesses 64113527 # DTB accesses
+system.cpu.itb.inst_hits 13699541 # ITB inst hits
+system.cpu.itb.inst_misses 12131 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2614 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2626 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 6917 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 6936 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 13622921 # ITB inst accesses
-system.cpu.itb.hits 13611127 # DTB hits
-system.cpu.itb.misses 11794 # DTB misses
-system.cpu.itb.accesses 13622921 # DTB accesses
-system.cpu.numCycles 414035717 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 13711672 # ITB inst accesses
+system.cpu.itb.hits 13699541 # DTB hits
+system.cpu.itb.misses 12131 # DTB misses
+system.cpu.itb.accesses 13711672 # DTB accesses
+system.cpu.numCycles 411150559 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 15526652 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 12489737 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 928336 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 10678484 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 8212324 # Number of BTB hits
+system.cpu.BPredUnit.lookups 15631672 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 12342234 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 929456 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 10552810 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 8288947 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1312295 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 195061 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 32929499 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 102163781 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 15526652 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9524619 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 22440538 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6579937 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 148688 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 93080203 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2936 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 137545 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 217702 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13603433 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 995292 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6599 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 153452703 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.827416 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.209875 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1323523 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 194787 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 32982972 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 102837345 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 15631672 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9612470 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 22590084 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6692504 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 158663 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 89850563 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2746 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 143204 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 218934 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 483 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 13691858 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 996334 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6838 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 150553763 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.848436 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.233477 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 131028378 85.39% 85.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1463837 0.95% 86.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1832687 1.19% 87.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2690815 1.75% 89.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1870921 1.22% 90.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1178749 0.77% 91.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2936419 1.91% 93.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 835625 0.54% 93.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9615272 6.27% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 127980574 85.01% 85.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1480097 0.98% 85.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1855620 1.23% 87.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2694532 1.79% 89.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1893570 1.26% 90.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1188011 0.79% 91.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2948135 1.96% 93.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 848652 0.56% 93.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 9664572 6.42% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 153452703 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.037501 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.246751 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 34954549 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 92988756 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 20078806 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1116855 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 4313737 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2248287 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 185454 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 119076129 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 599477 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 4313737 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 37045133 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36926846 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 49909637 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 19098925 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6158425 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 111441141 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 3427 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 975111 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4036126 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 44783 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 115828569 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 512776978 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 512681517 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 95461 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 77492759 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 38335809 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1177287 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1072928 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13010963 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 21488170 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 14015818 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1893787 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2361029 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 101216530 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1853504 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 125772492 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 220452 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 25469081 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 69618284 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 353864 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 153452703 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.819617 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.525568 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 150553763 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.038019 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.250121 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 35091688 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 89690975 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 20321625 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1025705 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4423770 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2273029 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 186320 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 119828190 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 605140 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 4423770 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 37165531 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37166387 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 46484492 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 19226681 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6086902 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 112339029 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 3754 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1012932 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4107831 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 44905 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 116884712 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 516607430 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 516512877 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 94553 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 77495227 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 39389484 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 939636 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 835400 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12435347 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 21635443 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 14050113 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1939177 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2494760 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 102209700 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1618930 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 126189021 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 231742 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 26205661 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 71388624 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 331981 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 150553763 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.838166 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.542583 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 107878797 70.30% 70.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 14731235 9.60% 79.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7302555 4.76% 84.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5766685 3.76% 88.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12704866 8.28% 96.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2797979 1.82% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1703854 1.11% 99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 430247 0.28% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 136485 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 105343416 69.97% 69.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 14065037 9.34% 79.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7354541 4.88% 84.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5909522 3.93% 88.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12758140 8.47% 96.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2807768 1.86% 98.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1730475 1.15% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 446826 0.30% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 138038 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 153452703 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 150553763 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 55588 0.63% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 3 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8410763 94.57% 95.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 427006 4.80% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 60599 0.68% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8416262 94.64% 95.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 416317 4.68% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 59380040 47.21% 47.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 95959 0.08% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 34 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 46 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2266 0.00% 47.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.38% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 53622551 42.63% 90.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12565056 9.99% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 59665616 47.28% 47.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 95635 0.08% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 36 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 48 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2270 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.44% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 53732100 42.58% 90.03% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12586768 9.97% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 125772492 # Type of FU issued
-system.cpu.iq.rate 0.303772 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8893360 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.070710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 414213065 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 128557320 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 86496982 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 24084 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 13214 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10457 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 134546484 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12838 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 592105 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 126189021 # Type of FU issued
+system.cpu.iq.rate 0.306917 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8893180 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.070475 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 412149363 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 130053896 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 86886822 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 24048 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 13080 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10409 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 134962848 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12823 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 636825 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5807721 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 11311 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 32412 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2237013 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 5953964 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 11249 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 33793 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2270680 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34115378 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1150417 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34115287 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1151875 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 4313737 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28451597 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 431255 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 103286909 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 337253 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 21488170 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 14015818 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1227531 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 94319 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 11225 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 32412 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 548239 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 349587 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 897826 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 122535537 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52641416 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3236955 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 4423770 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 28606306 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 435959 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 104089793 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 334839 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 21635443 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 14050113 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 991881 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 95881 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 11592 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 33793 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 550966 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 345374 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 896340 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 122956903 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52760819 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3232118 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 216875 # number of nop insts executed
-system.cpu.iew.exec_refs 65061832 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11533456 # Number of branches executed
-system.cpu.iew.exec_stores 12420416 # Number of stores executed
-system.cpu.iew.exec_rate 0.295954 # Inst execution rate
-system.cpu.iew.wb_sent 121007788 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 86507439 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 46901063 # num instructions producing a value
-system.cpu.iew.wb_consumers 86866563 # num instructions consuming a value
+system.cpu.iew.exec_nop 261163 # number of nop insts executed
+system.cpu.iew.exec_refs 65197273 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11589071 # Number of branches executed
+system.cpu.iew.exec_stores 12436454 # Number of stores executed
+system.cpu.iew.exec_rate 0.299056 # Inst execution rate
+system.cpu.iew.wb_sent 121403477 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 86897231 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47438485 # num instructions producing a value
+system.cpu.iew.wb_consumers 88321921 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.208937 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.539921 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.211351 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.537109 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 59599826 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 76939473 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 26171914 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1499640 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 790317 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 149221313 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.515606 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.482610 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 59601672 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 76942722 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 26965943 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1286949 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 790517 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 146212348 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.526240 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.505087 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 120951257 81.05% 81.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 14347270 9.61% 90.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4034652 2.70% 93.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2127712 1.43% 94.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1768055 1.18% 95.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1033434 0.69% 96.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1556613 1.04% 97.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 657865 0.44% 98.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2744455 1.84% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 118498573 81.05% 81.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13699176 9.37% 90.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3966547 2.71% 93.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2244227 1.53% 94.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1750329 1.20% 95.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1033206 0.71% 96.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1542131 1.05% 97.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 667633 0.46% 98.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2810526 1.92% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 149221313 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 59599826 # Number of instructions committed
-system.cpu.commit.committedOps 76939473 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 146212348 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 59601672 # Number of instructions committed
+system.cpu.commit.committedOps 76942722 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27459254 # Number of memory references committed
-system.cpu.commit.loads 15680449 # Number of loads committed
-system.cpu.commit.membars 413031 # Number of memory barriers committed
-system.cpu.commit.branches 9890920 # Number of branches committed
+system.cpu.commit.refs 27460912 # Number of memory references committed
+system.cpu.commit.loads 15681479 # Number of loads committed
+system.cpu.commit.membars 413077 # Number of memory barriers committed
+system.cpu.commit.branches 9891359 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 68492585 # Number of committed integer instructions.
-system.cpu.commit.function_calls 995546 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2744455 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 68495555 # Number of committed integer instructions.
+system.cpu.commit.function_calls 995632 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2810526 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 247831805 # The number of ROB reads
-system.cpu.rob.rob_writes 210661614 # The number of ROB writes
-system.cpu.timesIdled 1891867 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 260583014 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4592075418 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 59449445 # Number of Instructions Simulated
-system.cpu.committedOps 76789092 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 59449445 # Number of Instructions Simulated
-system.cpu.cpi 6.964501 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 6.964501 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.143585 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.143585 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 555570054 # number of integer regfile reads
-system.cpu.int_regfile_writes 88783658 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8868 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2963 # number of floating regfile writes
-system.cpu.misc_regfile_reads 134383864 # number of misc regfile reads
-system.cpu.misc_regfile_writes 912266 # number of misc regfile writes
-system.cpu.icache.replacements 1016880 # number of replacements
-system.cpu.icache.tagsinuse 511.619498 # Cycle average of tags in use
-system.cpu.icache.total_refs 12495254 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1017392 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 12.281652 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 6291400000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.619498 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.999257 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.999257 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 12495254 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 12495254 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 12495254 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 12495254 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 12495254 # number of overall hits
-system.cpu.icache.overall_hits::total 12495254 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1108036 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1108036 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1108036 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1108036 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1108036 # number of overall misses
-system.cpu.icache.overall_misses::total 1108036 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 16316535479 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 16316535479 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 16316535479 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 16316535479 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 16316535479 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 16316535479 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 13603290 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 13603290 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 13603290 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 13603290 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 13603290 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 13603290 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081454 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.081454 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.081454 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14725.636603 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14725.636603 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14725.636603 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 2951482 # number of cycles access was blocked
+system.cpu.rob.rob_reads 245553933 # The number of ROB reads
+system.cpu.rob.rob_writes 212368242 # The number of ROB writes
+system.cpu.timesIdled 1894262 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 260596796 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4592114044 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 59451291 # Number of Instructions Simulated
+system.cpu.committedOps 76792341 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 59451291 # Number of Instructions Simulated
+system.cpu.cpi 6.915755 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 6.915755 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.144597 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.144597 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 557431988 # number of integer regfile reads
+system.cpu.int_regfile_writes 89182974 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8912 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2994 # number of floating regfile writes
+system.cpu.misc_regfile_reads 135303561 # number of misc regfile reads
+system.cpu.misc_regfile_writes 912352 # number of misc regfile writes
+system.cpu.icache.replacements 1013837 # number of replacements
+system.cpu.icache.tagsinuse 511.616166 # Cycle average of tags in use
+system.cpu.icache.total_refs 12585526 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 1014349 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 12.407491 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 6289783000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 511.616166 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.999250 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.999250 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 12585526 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 12585526 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 12585526 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 12585526 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 12585526 # number of overall hits
+system.cpu.icache.overall_hits::total 12585526 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1106194 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1106194 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1106194 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1106194 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1106194 # number of overall misses
+system.cpu.icache.overall_misses::total 1106194 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 16291440480 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 16291440480 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 16291440480 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 16291440480 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 16291440480 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 16291440480 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 13691720 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 13691720 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 13691720 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 13691720 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 13691720 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 13691720 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080793 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.080793 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.080793 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14727.471384 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14727.471384 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14727.471384 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 3199983 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 405 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 416 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 7287.609877 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 7692.266827 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks::writebacks 58719 # number of writebacks
-system.cpu.icache.writebacks::total 58719 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90611 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 90611 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 90611 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 90611 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 90611 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 90611 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1017425 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1017425 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1017425 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1017425 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1017425 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1017425 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12153604482 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 12153604482 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12153604482 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 12153604482 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12153604482 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 12153604482 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7398500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7398500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7398500 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total 7398500 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11945.454930 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11945.454930 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11945.454930 # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks 59844 # number of writebacks
+system.cpu.icache.writebacks::total 59844 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91810 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 91810 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 91810 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 91810 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 91810 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 91810 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1014384 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 1014384 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 1014384 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 1014384 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 1014384 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 1014384 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12127535483 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 12127535483 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12127535483 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 12127535483 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12127535483 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 12127535483 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7292000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074087 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074087 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074087 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11955.566613 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11955.566613 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11955.566613 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 644925 # number of replacements
-system.cpu.dcache.tagsinuse 511.991557 # Cycle average of tags in use
-system.cpu.dcache.total_refs 21957407 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 645437 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 34.019443 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 49249000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.991557 # Average occupied blocks per requestor
+system.cpu.dcache.replacements 645435 # number of replacements
+system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use
+system.cpu.dcache.total_refs 22022963 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 645947 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 34.094071 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 49188000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.991565 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 14117520 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 14117520 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 7264910 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 7264910 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 285961 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 285961 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 285492 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 285492 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 21382430 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 21382430 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 21382430 # number of overall hits
-system.cpu.dcache.overall_hits::total 21382430 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 735373 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 735373 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2966010 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2966010 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 13726 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 13726 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 3701383 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3701383 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3701383 # number of overall misses
-system.cpu.dcache.overall_misses::total 3701383 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11086457500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11086457500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 110422837752 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 110422837752 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223704000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 223704000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 187500 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 187500 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 121509295252 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 121509295252 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 121509295252 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 121509295252 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 14852893 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 14852893 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10230920 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10230920 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299687 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 299687 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 285500 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 285500 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 25083813 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 25083813 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 25083813 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 25083813 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049510 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289906 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045801 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000028 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.147561 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.147561 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15075.964850 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37229.421935 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.828938 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 23437.500000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32828.079464 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32828.079464 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 16342936 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 7612500 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2868 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 5698.373780 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 28404.850746 # average number of cycles each access was blocked
+system.cpu.dcache.ReadReq_hits::cpu.data 14182326 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 14182326 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 7265741 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 7265741 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 285851 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 285851 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 285519 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 285519 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 21448067 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 21448067 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 21448067 # number of overall hits
+system.cpu.dcache.overall_hits::total 21448067 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 745935 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 745935 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2965804 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2965804 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 13758 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 13758 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 10 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 3711739 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3711739 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3711739 # number of overall misses
+system.cpu.dcache.overall_misses::total 3711739 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11230893500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 11230893500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 110142219264 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 110142219264 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224423500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 224423500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 267500 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 267500 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 121373112764 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 121373112764 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 121373112764 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 121373112764 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 14928261 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 14928261 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10231545 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10231545 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299609 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 299609 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 285529 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 285529 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 25159806 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 25159806 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 25159806 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 25159806 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049968 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289869 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045920 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000035 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.147527 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.147527 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15056.128885 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37137.389815 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16312.218346 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26750 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32699.797255 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32699.797255 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 16852944 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 7563500 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2993 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 267 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 5630.786502 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 28327.715356 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 574454 # number of writebacks
-system.cpu.dcache.writebacks::total 574454 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 348401 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 348401 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716534 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2716534 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1379 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1379 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3064935 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3064935 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3064935 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3064935 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386972 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 386972 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249476 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 249476 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12347 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12347 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 636448 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 636448 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 636448 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 636448 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5265104500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 5265104500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8925107436 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8925107436 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165722000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165722000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14190211936 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 14190211936 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14190211936 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 14190211936 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147157757000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147157757000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42274928970 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42274928970 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189432685970 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 189432685970 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026054 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024385 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041200 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025373 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025373 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13605.905595 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35775.415014 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13422.045841 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20312.500000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 575111 # number of writebacks
+system.cpu.dcache.writebacks::total 575111 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358347 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 358347 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716460 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2716460 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1395 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1395 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3074807 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3074807 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3074807 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3074807 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387588 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 387588 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249344 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 249344 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12363 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12363 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 10 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 636932 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 636932 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 636932 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 636932 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5281773000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 5281773000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8909514444 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8909514444 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 166180500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 166180500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 235000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 235000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14191287444 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 14191287444 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14191287444 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 14191287444 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147159264500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147159264500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42252638495 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42252638495 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189411902995 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 189411902995 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025963 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024370 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041264 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025315 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025315 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13627.287223 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35731.818067 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13441.761708 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23500 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22280.694712 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22280.694712 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1307788731818 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1307788731818 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1296055922339 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1296055922339 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 87981 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 87985 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:17:26
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 16:38:16
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 164277874000 because target called exit()
+Exiting @ tick 164248292500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.164278 # Number of seconds simulated
-sim_ticks 164277874000 # Number of ticks simulated
-final_tick 164277874000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.164248 # Number of seconds simulated
+sim_ticks 164248292500 # Number of ticks simulated
+final_tick 164248292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 203470 # Simulator instruction rate (inst/s)
-host_op_rate 215002 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 58636208 # Simulator tick rate (ticks/s)
-host_mem_usage 227276 # Number of bytes of host memory used
-host_seconds 2801.65 # Real time elapsed on the host
-sim_insts 570051643 # Number of instructions simulated
-sim_ops 602359850 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 5845952 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 50048 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 3721408 # Number of bytes written to this memory
-system.physmem.num_reads 91343 # Number of read requests responded to by this memory
-system.physmem.num_writes 58147 # Number of write requests responded to by this memory
+host_inst_rate 250614 # Simulator instruction rate (inst/s)
+host_op_rate 264817 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 72208895 # Simulator tick rate (ticks/s)
+host_mem_usage 224524 # Number of bytes of host memory used
+host_seconds 2274.63 # Real time elapsed on the host
+sim_insts 570052728 # Number of instructions simulated
+sim_ops 602360935 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 5850432 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 51136 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3722112 # Number of bytes written to this memory
+system.physmem.num_reads 91413 # Number of read requests responded to by this memory
+system.physmem.num_writes 58158 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 35585754 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 304655 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 22653130 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 58238884 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 35619439 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 311334 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 22661496 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 58280935 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
-system.cpu.numCycles 328555749 # number of cpu cycles simulated
+system.cpu.numCycles 328496586 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 85495228 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 80299392 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 2363839 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 47188450 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 46808758 # Number of BTB hits
+system.cpu.BPredUnit.lookups 85500889 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 80301573 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 2363462 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 47194810 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 46809578 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1441266 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 2064 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 68932526 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 669692235 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 85495228 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 48250024 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 130038876 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 13469589 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 117716369 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 673 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 67498352 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 807371 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 327717199 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.177607 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.200173 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1441693 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 2047 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 68928725 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 669724193 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 85500889 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 48251271 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 130040939 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 13471504 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 117632066 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 466 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 67495318 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 807242 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 327633093 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.178244 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.200456 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 197678537 60.32% 60.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 20955398 6.39% 66.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 4944268 1.51% 68.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 14317146 4.37% 72.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 8982056 2.74% 75.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 9405272 2.87% 78.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 4386310 1.34% 79.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 5814100 1.77% 81.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 61234112 18.69% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 197592366 60.31% 60.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 20955363 6.40% 66.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 4944852 1.51% 68.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 14316797 4.37% 72.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 8978717 2.74% 75.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 9406752 2.87% 78.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 4386482 1.34% 79.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 5812411 1.77% 81.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 61239353 18.69% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 327717199 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.260215 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.038291 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 93143264 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 94872868 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 108628769 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 20045238 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 11027060 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4784060 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 1759 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 705973468 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 5432 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 11027060 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 107429081 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 13945008 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 118563 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 114317154 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 80880333 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 697178999 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 231 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 59283430 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 19375407 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 624 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 723780453 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3241174730 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3241174602 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 327633093 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.260279 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.038755 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 93122772 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 94805335 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 108615724 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 20060132 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 11029130 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4785077 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 1812 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 705993706 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 5866 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 11029130 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 107405098 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 13994903 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 53643 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 114322395 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 80827924 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 697209083 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 245 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 59229209 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 19383033 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 653 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 723812839 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3241314962 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3241314834 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 627417466 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 96362987 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 11553 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 11552 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 169904976 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 172902366 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 80616631 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 21434396 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 27805052 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 681951411 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 9116 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 646829241 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1424329 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 79415012 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 197703011 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 2761 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 327717199 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.973742 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.738606 # Number of insts issued each cycle
+system.cpu.rename.CommittedMaps 627419202 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 96393637 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 6694 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 6687 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 169956085 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 172904405 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 80621547 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 21577919 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 28225780 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 681971655 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 4856 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 646826004 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1423990 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 79433587 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 197870891 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1925 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 327633093 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.974239 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.736392 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 68508405 20.90% 20.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 84956160 25.92% 46.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 75144846 22.93% 69.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 40581693 12.38% 82.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 28626833 8.74% 90.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15169754 4.63% 95.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 5928523 1.81% 97.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 6496810 1.98% 99.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2304175 0.70% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 68428283 20.89% 20.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 84743637 25.87% 46.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 75345420 23.00% 69.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 40565003 12.38% 82.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 28664322 8.75% 90.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15213545 4.64% 95.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 5876273 1.79% 97.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 6659013 2.03% 99.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2137597 0.65% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 327717199 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 327633093 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 204843 5.11% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2907010 72.53% 77.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 896423 22.36% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 205009 5.12% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2904405 72.49% 77.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 897167 22.39% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 403920439 62.45% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 6568 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 403920644 62.45% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 6585 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 166108811 25.68% 88.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 76793420 11.87% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 166111461 25.68% 88.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 76787311 11.87% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 646829241 # Type of FU issued
-system.cpu.iq.rate 1.968705 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 4008276 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006197 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1626808250 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 761386923 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 638549644 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 646826004 # Type of FU issued
+system.cpu.iq.rate 1.969049 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 4006581 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006194 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1626715636 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 761421594 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 638533475 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 650837497 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 650832565 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 30424903 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 30420680 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 23949762 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 129784 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11648 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 10395608 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 23951584 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 127945 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 11724 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 10400307 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 12818 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 12531 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 12832 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 12549 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 11027060 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 853408 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 62572 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 682026706 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 660555 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 172902366 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 80616631 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 7782 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 13060 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 6245 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11648 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1315368 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1582506 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 2897874 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 642687405 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 163985784 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 4141836 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 11029130 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 827373 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 62655 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 682042744 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 662438 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 172904405 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 80621547 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 3504 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 13090 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 6258 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 11724 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1313555 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1583724 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 2897279 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 642671991 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 163979527 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 4154013 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 66179 # number of nop insts executed
-system.cpu.iew.exec_refs 239997187 # number of memory reference insts executed
-system.cpu.iew.exec_branches 74667058 # Number of branches executed
-system.cpu.iew.exec_stores 76011403 # Number of stores executed
-system.cpu.iew.exec_rate 1.956098 # Inst execution rate
-system.cpu.iew.wb_sent 640040588 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 638549660 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 420197588 # num instructions producing a value
-system.cpu.iew.wb_consumers 654962025 # num instructions consuming a value
+system.cpu.iew.exec_nop 66233 # number of nop insts executed
+system.cpu.iew.exec_refs 239982954 # number of memory reference insts executed
+system.cpu.iew.exec_branches 74668739 # Number of branches executed
+system.cpu.iew.exec_stores 76003427 # Number of stores executed
+system.cpu.iew.exec_rate 1.956404 # Inst execution rate
+system.cpu.iew.wb_sent 640027985 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 638533491 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 420151811 # num instructions producing a value
+system.cpu.iew.wb_consumers 654946950 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.943505 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.641560 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.943806 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.641505 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 570051694 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 602359901 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 79676133 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 6355 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2424230 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 316690140 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.902048 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.239406 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 570052779 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 602360986 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 79691237 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 2423863 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 316603964 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.902569 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.239613 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 92731092 29.28% 29.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 104002875 32.84% 62.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 43058477 13.60% 75.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 8922442 2.82% 78.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 25674548 8.11% 86.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 13103987 4.14% 90.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 7582493 2.39% 93.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1154147 0.36% 93.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 20460079 6.46% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 92664555 29.27% 29.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 103983968 32.84% 62.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 43054287 13.60% 75.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 8920631 2.82% 78.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 25673085 8.11% 86.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 13110941 4.14% 90.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 7578873 2.39% 93.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1154724 0.36% 93.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 20462900 6.46% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 316690140 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 570051694 # Number of instructions committed
-system.cpu.commit.committedOps 602359901 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 316603964 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 570052779 # Number of instructions committed
+system.cpu.commit.committedOps 602360986 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 219173627 # Number of memory references committed
-system.cpu.commit.loads 148952604 # Number of loads committed
+system.cpu.commit.refs 219174061 # Number of memory references committed
+system.cpu.commit.loads 148952821 # Number of loads committed
system.cpu.commit.membars 1328 # Number of memory barriers committed
-system.cpu.commit.branches 70828611 # Number of branches committed
+system.cpu.commit.branches 70828828 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 533522679 # Number of committed integer instructions.
+system.cpu.commit.int_insts 533523547 # Number of committed integer instructions.
system.cpu.commit.function_calls 997573 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 20460079 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 20462900 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 978265483 # The number of ROB reads
-system.cpu.rob.rob_writes 1375131668 # The number of ROB writes
-system.cpu.timesIdled 36876 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 838550 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 570051643 # Number of Instructions Simulated
-system.cpu.committedOps 602359850 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 570051643 # Number of Instructions Simulated
-system.cpu.cpi 0.576361 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.576361 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.735023 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.735023 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3210434144 # number of integer regfile reads
-system.cpu.int_regfile_writes 664206400 # number of integer regfile writes
+system.cpu.rob.rob_reads 978192675 # The number of ROB reads
+system.cpu.rob.rob_writes 1375166180 # The number of ROB writes
+system.cpu.timesIdled 37006 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 863493 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 570052728 # Number of Instructions Simulated
+system.cpu.committedOps 602360935 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 570052728 # Number of Instructions Simulated
+system.cpu.cpi 0.576256 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.576256 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.735338 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.735338 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3210352058 # number of integer regfile reads
+system.cpu.int_regfile_writes 664199500 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 905030713 # number of misc regfile reads
-system.cpu.misc_regfile_writes 2676 # number of misc regfile writes
-system.cpu.icache.replacements 62 # number of replacements
-system.cpu.icache.tagsinuse 695.805278 # Cycle average of tags in use
-system.cpu.icache.total_refs 67497251 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 819 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 82414.225885 # Average number of references to valid blocks.
+system.cpu.misc_regfile_reads 905055598 # number of misc regfile reads
+system.cpu.misc_regfile_writes 3110 # number of misc regfile writes
+system.cpu.icache.replacements 66 # number of replacements
+system.cpu.icache.tagsinuse 704.852693 # Cycle average of tags in use
+system.cpu.icache.total_refs 67494169 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 836 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 80734.651914 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 695.805278 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.339749 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.339749 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 67497251 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 67497251 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 67497251 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 67497251 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 67497251 # number of overall hits
-system.cpu.icache.overall_hits::total 67497251 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1101 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1101 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1101 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1101 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1101 # number of overall misses
-system.cpu.icache.overall_misses::total 1101 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 37785500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 37785500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 37785500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 37785500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 37785500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 37785500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 67498352 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 67498352 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 67498352 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 67498352 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 67498352 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 67498352 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34319.255223 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 34319.255223 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 34319.255223 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 704.852693 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.344166 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.344166 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 67494169 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 67494169 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 67494169 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 67494169 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 67494169 # number of overall hits
+system.cpu.icache.overall_hits::total 67494169 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1149 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1149 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1149 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1149 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1149 # number of overall misses
+system.cpu.icache.overall_misses::total 1149 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 39292000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 39292000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 39292000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 39292000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 39292000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 39292000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 67495318 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 67495318 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 67495318 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 67495318 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 67495318 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 67495318 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34196.692776 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 34196.692776 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 34196.692776 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 282 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 282 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 282 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 282 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 282 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 282 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27945500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 27945500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27945500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 27945500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27945500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 27945500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 310 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 310 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 310 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 310 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 839 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 839 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 839 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 839 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 839 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28616000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 28616000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28616000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 28616000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28616000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 28616000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34121.489621 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34121.489621 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34121.489621 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34107.270560 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34107.270560 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34107.270560 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 440502 # number of replacements
-system.cpu.dcache.tagsinuse 4094.647718 # Cycle average of tags in use
-system.cpu.dcache.total_refs 199930074 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 444598 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 449.687300 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 88231000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4094.647718 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999670 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999670 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 132066425 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 132066425 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 67860846 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 67860846 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 1466 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 1466 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 1337 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 1337 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 199927271 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 199927271 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 199927271 # number of overall hits
-system.cpu.dcache.overall_hits::total 199927271 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 249429 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 249429 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1556685 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1556685 # number of WriteReq misses
+system.cpu.dcache.replacements 440506 # number of replacements
+system.cpu.dcache.tagsinuse 4094.673413 # Cycle average of tags in use
+system.cpu.dcache.total_refs 199917627 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 444602 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 449.655258 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 87177000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4094.673413 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999676 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999676 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 132064751 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 132064751 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 67849620 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 67849620 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 1690 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 1690 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 1554 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 199914371 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 199914371 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 199914371 # number of overall hits
+system.cpu.dcache.overall_hits::total 199914371 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 249324 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 249324 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1567911 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1567911 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 16 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 16 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 1806114 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1806114 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1806114 # number of overall misses
-system.cpu.dcache.overall_misses::total 1806114 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3287429500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3287429500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 27038709023 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 27038709023 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 163500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 163500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 30326138523 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 30326138523 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 30326138523 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 30326138523 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 132315854 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 132315854 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 1817235 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1817235 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1817235 # number of overall misses
+system.cpu.dcache.overall_misses::total 1817235 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 3293272500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 3293272500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 27061002013 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 27061002013 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 203000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 203000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 30354274513 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 30354274513 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 30354274513 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 30354274513 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 132314075 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 132314075 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1482 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 1482 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 1337 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 1337 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 201733385 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 201733385 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 201733385 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 201733385 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001885 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022425 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.010796 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.008953 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.008953 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13179.820711 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17369.415793 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10218.750000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16790.821910 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16790.821910 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 9531023 # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1706 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 1706 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 1554 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 201731606 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 201731606 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 201731606 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 201731606 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001884 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022587 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.009379 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.009008 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.009008 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13208.806613 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17259.271740 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12687.500000 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16703.549355 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16703.549355 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 9569014 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2188 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2180 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 4356.043419 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 4389.455963 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 394920 # number of writebacks
-system.cpu.dcache.writebacks::total 394920 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51943 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 51943 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1309572 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1309572 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 394908 # number of writebacks
+system.cpu.dcache.writebacks::total 394908 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51828 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 51828 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1320801 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1320801 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 16 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 16 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1361515 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1361515 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1361515 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1361515 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197486 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 197486 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247113 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 247113 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 444599 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 444599 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 444599 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 444599 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1627372000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 1627372000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2541087023 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2541087023 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4168459023 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 4168459023 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4168459023 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 4168459023 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data 1372629 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1372629 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1372629 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1372629 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197496 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 197496 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247110 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 247110 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 444606 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 444606 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 444606 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 444606 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1630743000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 1630743000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2541828513 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2541828513 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4172571513 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 4172571513 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4172571513 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 4172571513 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001493 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8240.442360 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10283.097300 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9375.772377 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9375.772377 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8257.093815 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10286.222787 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9384.874502 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9384.874502 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 73147 # number of replacements
-system.cpu.l2cache.tagsinuse 17814.593774 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 421447 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 88664 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 4.753305 # Average number of references to valid blocks.
+system.cpu.l2cache.replacements 73212 # number of replacements
+system.cpu.l2cache.tagsinuse 17814.608666 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 421435 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 88732 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 4.749527 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 15926.190244 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 37.609584 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 1850.793945 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.486029 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.001148 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.056482 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.543658 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 37 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 165212 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 165249 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 394920 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 394920 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 188816 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 188816 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 37 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 354028 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 354065 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 37 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 354028 # number of overall hits
-system.cpu.l2cache.overall_hits::total 354065 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 782 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 32272 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 33054 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 58299 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 58299 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 782 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 90571 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 91353 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 782 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 90571 # number of overall misses
-system.cpu.l2cache.overall_misses::total 91353 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26847500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1107385000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 1134232500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2000629500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 2000629500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 26847500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 3108014500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 3134862000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 26847500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 3108014500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 3134862000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 819 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 197484 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 198303 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 394920 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 394920 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 247115 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 247115 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 819 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 444599 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 445418 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 819 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 444599 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 445418 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.954823 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163416 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235918 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.954823 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.203714 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954823 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.203714 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.841432 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34314.111304 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34316.703546 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.841432 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34315.779885 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.841432 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34315.779885 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 1901500 # number of cycles access was blocked
+system.cpu.l2cache.occ_blocks::writebacks 15925.956754 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 38.298458 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1850.353454 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.486022 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.001169 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.056468 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.543659 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 36 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 165185 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 165221 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 394908 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 394908 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 188795 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 188795 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 36 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 353980 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 354016 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 36 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 353980 # number of overall hits
+system.cpu.l2cache.overall_hits::total 354016 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 800 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 32306 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 33106 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 58317 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 58317 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 800 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 90623 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 91423 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 800 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 90623 # number of overall misses
+system.cpu.l2cache.overall_misses::total 91423 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27465500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1108067500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1135533000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2001435500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2001435500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 27465500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 3109503000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 3136968500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 27465500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 3109503000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 3136968500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 836 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 197491 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 198327 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 394908 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 394908 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 247112 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 247112 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 836 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 444603 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 445439 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 836 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 444603 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 445439 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.956938 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163582 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235994 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.956938 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.203829 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.956938 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.203829 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.875000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34299.124002 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34319.932438 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.875000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34312.514483 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.875000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34312.514483 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 2005000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 340 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 332 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5592.647059 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6039.156627 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 58147 # number of writebacks
-system.cpu.l2cache.writebacks::total 58147 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks 58158 # number of writebacks
+system.cpu.l2cache.writebacks::total 58158 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 782 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32262 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 33044 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58299 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 58299 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 782 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 90561 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 91343 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 782 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 90561 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 91343 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24334000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1002753500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1027087500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1820295000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1820295000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24334000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2823048500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 2847382500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24334000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2823048500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 2847382500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.954823 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163365 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235918 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954823 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203691 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954823 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203691 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31117.647059 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31081.566549 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31223.434364 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31117.647059 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31172.894513 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31117.647059 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31172.894513 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 799 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32297 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 33096 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58317 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 58317 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 799 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 90614 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 91413 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 799 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 90614 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 91413 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24875000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1003961000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028836000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1821234000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1821234000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24875000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2825195000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 2850070000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24875000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2825195000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 2850070000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163537 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235994 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203809 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203809 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31132.665832 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31085.271078 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31229.898657 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31132.665832 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31178.349924 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31132.665832 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31178.349924 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 15:43:07
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 16:54:39
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 301191370000 # Number of ticks simulated
final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3323130 # Simulator instruction rate (inst/s)
-host_op_rate 3511472 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1755802369 # Simulator tick rate (ticks/s)
-host_mem_usage 216428 # Number of bytes of host memory used
-host_seconds 171.54 # Real time elapsed on the host
+host_inst_rate 2848986 # Simulator instruction rate (inst/s)
+host_op_rate 3010454 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1505284316 # Simulator tick rate (ticks/s)
+host_mem_usage 213580 # Number of bytes of host memory used
+host_seconds 200.09 # Real time elapsed on the host
sim_insts 570051644 # Number of instructions simulated
sim_ops 602359851 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 2680160157 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 1993546 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 67018854 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls
system.cpu.num_int_insts 533522639 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2770243005 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 15:45:54
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 16:58:09
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 796762926000 # Number of ticks simulated
final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1880906 # Simulator instruction rate (inst/s)
-host_op_rate 1986306 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2635941289 # Simulator tick rate (ticks/s)
-host_mem_usage 225340 # Number of bytes of host memory used
-host_seconds 302.27 # Real time elapsed on the host
+host_inst_rate 2008356 # Simulator instruction rate (inst/s)
+host_op_rate 2120897 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2814551305 # Simulator tick rate (ticks/s)
+host_mem_usage 222752 # Number of bytes of host memory used
+host_seconds 283.09 # Real time elapsed on the host
sim_insts 568539343 # Number of instructions simulated
sim_ops 600398281 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5759488 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 1993546 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 67018854 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls
system.cpu.num_int_insts 533522639 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:17:26
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:02:50
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 30004011500 because target called exit()
+Exiting @ tick 25988864000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.030004 # Number of seconds simulated
-sim_ticks 30004011500 # Number of ticks simulated
-final_tick 30004011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.025989 # Number of seconds simulated
+sim_ticks 25988864000 # Number of ticks simulated
+final_tick 25988864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 194545 # Simulator instruction rate (inst/s)
-host_op_rate 195941 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 64427791 # Simulator tick rate (ticks/s)
-host_mem_usage 360100 # Number of bytes of host memory used
-host_seconds 465.70 # Real time elapsed on the host
-sim_insts 90599351 # Number of instructions simulated
-sim_ops 91249905 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 997760 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 45184 # Number of instructions bytes read from this memory
+host_inst_rate 238212 # Simulator instruction rate (inst/s)
+host_op_rate 239922 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 68332245 # Simulator tick rate (ticks/s)
+host_mem_usage 357212 # Number of bytes of host memory used
+host_seconds 380.33 # Real time elapsed on the host
+sim_insts 90599356 # Number of instructions simulated
+sim_ops 91249910 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 999040 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 46144 # Number of instructions bytes read from this memory
system.physmem.bytes_written 2048 # Number of bytes written to this memory
-system.physmem.num_reads 15590 # Number of read requests responded to by this memory
+system.physmem.num_reads 15610 # Number of read requests responded to by this memory
system.physmem.num_writes 32 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 33254220 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 1505932 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 68258 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 33322478 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 38441080 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1775530 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 78803 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 38519883 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 60008024 # number of cpu cycles simulated
+system.cpu.numCycles 51977729 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 26814888 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 22097408 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 908993 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 11644795 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 11349875 # Number of BTB hits
+system.cpu.BPredUnit.lookups 27100787 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 22324909 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 913851 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 11625204 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 11498872 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 60971 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 9988 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 14353439 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 128015722 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 26814888 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 11410846 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 24114191 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4769366 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 17672895 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 61157 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 10323 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 14508615 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 130146910 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 27100787 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 11560029 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 24493529 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4999674 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 8879281 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1085 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 13983254 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 369829 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 59980295 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.152543 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.127200 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 50 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 14156722 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 388066 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 51938784 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.527703 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.247354 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 35906918 59.86% 59.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3423177 5.71% 65.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2008077 3.35% 68.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1555866 2.59% 71.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1665852 2.78% 74.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2959461 4.93% 79.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1530954 2.55% 81.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1083113 1.81% 83.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9846877 16.42% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 27487299 52.92% 52.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3456218 6.65% 59.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2037280 3.92% 63.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1594827 3.07% 66.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1702478 3.28% 69.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2979904 5.74% 75.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1536396 2.96% 78.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1112311 2.14% 80.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 10032071 19.32% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 59980295 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.446855 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.133310 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 17244522 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 15439127 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 22437836 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1028996 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3829814 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4444165 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 8973 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 126393401 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 43020 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3829814 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 19245787 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2026344 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 8384525 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 21437306 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5056519 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 122679258 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 280519 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 3795375 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 346 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 142938307 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 534568737 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 534562281 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 6456 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 107429471 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 35508836 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 621620 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 624255 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13585300 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29418557 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5501060 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1379571 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 681227 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 117000498 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 611217 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 104991352 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 35829 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 26158745 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 64243821 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 56369 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 59980295 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.750431 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.873941 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 51938784 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.521392 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.503898 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 17258666 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 6822276 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 22930941 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 878432 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4048469 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4484484 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 8960 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 128309268 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 42973 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 4048469 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 19038937 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2026641 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 195067 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 21988132 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4641538 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 124853766 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 286024 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 3901771 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 441 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 145615724 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 543819179 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 543813062 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 6117 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 107429479 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 38186245 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 20008 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 20006 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 11296413 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 29738779 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 5601526 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2062082 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1203344 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 119239629 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 22672 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 105633795 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 86270 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 27804178 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 69103102 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 12544 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 51938784 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.033813 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.918657 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 20705588 34.52% 34.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13184290 21.98% 56.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8487470 14.15% 70.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6459646 10.77% 81.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4931435 8.22% 89.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2870978 4.79% 94.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2481638 4.14% 98.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 391274 0.65% 99.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 467976 0.78% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 14084713 27.12% 27.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 11449450 22.04% 49.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 8003608 15.41% 64.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6710442 12.92% 77.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 5305637 10.22% 87.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2900837 5.59% 93.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2546575 4.90% 98.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 460556 0.89% 99.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 476966 0.92% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 59980295 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 51938784 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 31457 4.81% 4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 27 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 343779 52.58% 57.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 278563 42.61% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 33927 5.08% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 27 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 354815 53.12% 58.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 279170 41.80% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 74214604 70.69% 70.69% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10958 0.01% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 3 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 201 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 251 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25591383 24.37% 95.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5173950 4.93% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 74740578 70.75% 70.75% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 10525 0.01% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 195 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 237 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.76% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 25722669 24.35% 95.12% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 5159588 4.88% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 104991352 # Type of FU issued
-system.cpu.iq.rate 1.749622 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 653826 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006227 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 270651681 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 143770389 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 102345485 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 973 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1384 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 418 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 105644695 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 483 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 378050 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 105633795 # Type of FU issued
+system.cpu.iq.rate 2.032290 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 667939 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006323 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 263959647 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 147067415 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 102938725 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 936 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1347 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 404 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 106301267 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 467 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 423068 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 6842681 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 23943 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 1595 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 754307 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 7162902 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 8413 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 3100 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 854772 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 497 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 30477 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 39235 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3829814 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 196269 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 34070 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 117648153 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 398714 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29418557 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5501060 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 607315 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 13787 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1140 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 1595 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 486496 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 484094 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 970590 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 103957070 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25266637 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1034282 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 4048469 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 193737 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 33246 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 119298911 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 399459 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 29738779 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 5601526 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 18769 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 13636 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 1014 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 3100 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 499711 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 490212 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 989923 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 104558374 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25377273 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1075421 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 36438 # number of nop insts executed
-system.cpu.iew.exec_refs 30369134 # number of memory reference insts executed
-system.cpu.iew.exec_branches 21275406 # Number of branches executed
-system.cpu.iew.exec_stores 5102497 # Number of stores executed
-system.cpu.iew.exec_rate 1.732386 # Inst execution rate
-system.cpu.iew.wb_sent 102646599 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 102345903 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 60560786 # num instructions producing a value
-system.cpu.iew.wb_consumers 98602756 # num instructions consuming a value
+system.cpu.iew.exec_nop 36610 # number of nop insts executed
+system.cpu.iew.exec_refs 30470186 # number of memory reference insts executed
+system.cpu.iew.exec_branches 21355608 # Number of branches executed
+system.cpu.iew.exec_stores 5092913 # Number of stores executed
+system.cpu.iew.exec_rate 2.011600 # Inst execution rate
+system.cpu.iew.wb_sent 103258351 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 102939129 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 62202150 # num instructions producing a value
+system.cpu.iew.wb_consumers 103963576 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.705537 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.614190 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.980447 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.598307 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 90611960 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 91262514 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 26386952 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 554848 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 912021 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 56150482 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.625320 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.343724 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 90611965 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 91262519 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 28037719 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 10128 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 916929 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 47890316 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.905657 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.507554 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 23848704 42.47% 42.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 15483848 27.58% 70.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4738925 8.44% 78.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3887159 6.92% 85.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1619823 2.88% 88.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 955795 1.70% 90.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 662165 1.18% 91.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 224422 0.40% 91.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 4729641 8.42% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 17540600 36.63% 36.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13534361 28.26% 64.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4502880 9.40% 74.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 3873758 8.09% 82.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1516151 3.17% 85.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 799389 1.67% 87.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 846315 1.77% 88.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 253211 0.53% 89.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5023651 10.49% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 56150482 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 90611960 # Number of instructions committed
-system.cpu.commit.committedOps 91262514 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 47890316 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 90611965 # Number of instructions committed
+system.cpu.commit.committedOps 91262519 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27322629 # Number of memory references committed
-system.cpu.commit.loads 22575876 # Number of loads committed
+system.cpu.commit.refs 27322631 # Number of memory references committed
+system.cpu.commit.loads 22575877 # Number of loads committed
system.cpu.commit.membars 3888 # Number of memory barriers committed
-system.cpu.commit.branches 18722470 # Number of branches committed
+system.cpu.commit.branches 18722471 # Number of branches committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 72533318 # Number of committed integer instructions.
+system.cpu.commit.int_insts 72533322 # Number of committed integer instructions.
system.cpu.commit.function_calls 56148 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 4729641 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5023651 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 169064573 # The number of ROB reads
-system.cpu.rob.rob_writes 239150312 # The number of ROB writes
-system.cpu.timesIdled 1544 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 27729 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 90599351 # Number of Instructions Simulated
-system.cpu.committedOps 91249905 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 90599351 # Number of Instructions Simulated
-system.cpu.cpi 0.662345 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.662345 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.509787 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.509787 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 494492343 # number of integer regfile reads
-system.cpu.int_regfile_writes 120192106 # number of integer regfile writes
-system.cpu.fp_regfile_reads 207 # number of floating regfile reads
-system.cpu.fp_regfile_writes 538 # number of floating regfile writes
-system.cpu.misc_regfile_reads 181239075 # number of misc regfile reads
-system.cpu.misc_regfile_writes 11602 # number of misc regfile writes
+system.cpu.rob.rob_reads 162161169 # The number of ROB reads
+system.cpu.rob.rob_writes 242671240 # The number of ROB writes
+system.cpu.timesIdled 1828 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 38945 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 90599356 # Number of Instructions Simulated
+system.cpu.committedOps 91249910 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 90599356 # Number of Instructions Simulated
+system.cpu.cpi 0.573710 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.573710 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.743042 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.743042 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 497076309 # number of integer regfile reads
+system.cpu.int_regfile_writes 120895703 # number of integer regfile writes
+system.cpu.fp_regfile_reads 198 # number of floating regfile reads
+system.cpu.fp_regfile_writes 527 # number of floating regfile writes
+system.cpu.misc_regfile_reads 183813486 # number of misc regfile reads
+system.cpu.misc_regfile_writes 11604 # number of misc regfile writes
system.cpu.icache.replacements 3 # number of replacements
-system.cpu.icache.tagsinuse 625.228438 # Cycle average of tags in use
-system.cpu.icache.total_refs 13982297 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 731 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 19127.629275 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 649.670012 # Cycle average of tags in use
+system.cpu.icache.total_refs 14155750 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 749 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 18899.532710 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 625.228438 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.305287 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.305287 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 13982297 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 13982297 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 13982297 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 13982297 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 13982297 # number of overall hits
-system.cpu.icache.overall_hits::total 13982297 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses
-system.cpu.icache.overall_misses::total 957 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 33318000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 33318000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 33318000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 33318000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 33318000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 33318000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 13983254 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 13983254 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 13983254 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 13983254 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 13983254 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 13983254 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000068 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000068 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000068 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34815.047022 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 34815.047022 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 34815.047022 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 649.670012 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.317222 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.317222 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 14155750 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 14155750 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 14155750 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 14155750 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 14155750 # number of overall hits
+system.cpu.icache.overall_hits::total 14155750 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 972 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 972 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 972 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 972 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 972 # number of overall misses
+system.cpu.icache.overall_misses::total 972 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 33892500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 33892500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 33892500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 33892500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 33892500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 33892500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 14156722 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 14156722 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 14156722 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 14156722 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 14156722 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 14156722 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000069 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000069 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34868.827160 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 226 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 226 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 226 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 226 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 731 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 731 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 731 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 731 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 731 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 731 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25047000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 25047000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25047000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 25047000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25047000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 25047000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34264.021888 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34264.021888 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34264.021888 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 223 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 223 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 223 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 749 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 749 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 749 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 749 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 749 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25625000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 25625000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25625000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 25625000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25625000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 25625000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34212.283044 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 943524 # number of replacements
-system.cpu.dcache.tagsinuse 3583.229064 # Cycle average of tags in use
-system.cpu.dcache.total_refs 28391066 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 947620 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 29.960391 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 10655820000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3583.229064 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.874812 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.874812 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 23819030 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23819030 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4560353 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4560353 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 5887 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 5887 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 5796 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 5796 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 28379383 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 28379383 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 28379383 # number of overall hits
-system.cpu.dcache.overall_hits::total 28379383 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 991638 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 991638 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 174628 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 174628 # number of WriteReq misses
+system.cpu.dcache.replacements 943602 # number of replacements
+system.cpu.dcache.tagsinuse 3646.405021 # Cycle average of tags in use
+system.cpu.dcache.total_refs 28436874 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 947698 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 30.006261 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 8214901000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 3646.405021 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.890236 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.890236 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 23866253 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 23866253 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 4558926 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 4558926 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 5898 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 5898 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 5797 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 5797 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 28425179 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 28425179 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 28425179 # number of overall hits
+system.cpu.dcache.overall_hits::total 28425179 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1004103 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1004103 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 176055 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 176055 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 1166266 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1166266 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1166266 # number of overall misses
-system.cpu.dcache.overall_misses::total 1166266 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 5615598500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 5615598500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4530256968 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4530256968 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 129500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 129500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 10145855468 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 10145855468 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 10145855468 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 10145855468 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 24810668 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 24810668 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 1180158 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1180158 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1180158 # number of overall misses
+system.cpu.dcache.overall_misses::total 1180158 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 5784178500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 5784178500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4612267011 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4612267011 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 129000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 129000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 10396445511 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 10396445511 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 10396445511 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 10396445511 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 24870356 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 24870356 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5895 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 5895 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 5796 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 5796 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 29545649 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 29545649 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 29545649 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 29545649 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039968 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.036880 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001357 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.039473 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.039473 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5662.952106 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25942.328653 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16187.500000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 8699.435179 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 8699.435179 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 23124041 # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5906 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 5906 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 5797 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 5797 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 29605337 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 29605337 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 29605337 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 29605337 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040373 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037182 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001355 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.039863 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.039863 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5760.542992 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26197.875726 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16125 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 23104055 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 8085 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 8078 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.116388 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.120698 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 942876 # number of writebacks
-system.cpu.dcache.writebacks::total 942876 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87943 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 87943 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 130703 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 130703 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 942908 # number of writebacks
+system.cpu.dcache.writebacks::total 942908 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 99918 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 99918 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 132542 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 132542 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 218646 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 218646 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 218646 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 218646 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903695 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 903695 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43925 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 43925 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 947620 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 947620 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 947620 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 947620 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2331156500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2331156500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1079888101 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1079888101 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3411044601 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 3411044601 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3411044601 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 3411044601 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036424 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009277 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032073 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032073 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2579.583266 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24584.817325 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3599.591187 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3599.591187 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data 232460 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 232460 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 232460 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 232460 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904185 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 904185 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43513 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 43513 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 947698 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 947698 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 947698 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 947698 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2402147500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2402147500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1077084130 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1077084130 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3479231630 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 3479231630 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3479231630 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 3479231630 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036356 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009190 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2656.699127 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24753.157217 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 759 # number of replacements
-system.cpu.l2cache.tagsinuse 9484.092590 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1597486 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 15574 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 102.573905 # Average number of references to valid blocks.
+system.cpu.l2cache.replacements 770 # number of replacements
+system.cpu.l2cache.tagsinuse 10017.166349 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1600694 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 15595 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 102.641488 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 9095.853613 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 194.259268 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 193.979709 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.277583 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.005928 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.005920 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.289432 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 902114 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 902138 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 942876 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 942876 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 30612 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 30612 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 932726 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 932750 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 932726 # number of overall hits
-system.cpu.l2cache.overall_hits::total 932750 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 707 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 356 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 1063 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 707 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 14894 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 15601 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 707 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 14894 # number of overall misses
-system.cpu.l2cache.overall_misses::total 15601 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24231000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12178500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 36409500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 499418000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 499418000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 24231000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 511596500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 535827500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 24231000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 511596500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 535827500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 731 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 902470 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 903201 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 942876 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 942876 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 45150 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 45150 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 731 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 947620 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 948351 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 731 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 947620 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 948351 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967168 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000394 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.321993 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967168 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.015717 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967168 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.015717 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34272.984441 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34209.269663 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34352.593204 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34272.984441 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34349.167450 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34272.984441 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34349.167450 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 9634.775304 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 182.147356 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 200.243688 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.294030 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.005559 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.006111 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.305700 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 902746 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 902773 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 942908 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 942908 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 30054 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 30054 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 932800 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 932827 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 932800 # number of overall hits
+system.cpu.l2cache.overall_hits::total 932827 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 364 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 1086 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 14534 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 14534 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 722 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 14898 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 15620 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 722 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 14898 # number of overall misses
+system.cpu.l2cache.overall_misses::total 15620 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24755500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12471500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 37227000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 499277500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 499277500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 24755500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 511749000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 536504500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 24755500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 511749000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 536504500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 749 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 903110 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 903859 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 942908 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 942908 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 44588 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 44588 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 749 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 947698 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 948447 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 749 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 947698 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 948447 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963952 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000403 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.325962 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963952 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.015720 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963952 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.015720 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34287.396122 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34262.362637 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34352.380625 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks
system.cpu.l2cache.writebacks::total 32 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 706 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 346 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1052 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 706 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 14884 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 15590 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 706 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 14884 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 15590 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21938500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10782000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32720500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 452176000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 452176000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21938500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 462958000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 484896500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21938500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 462958000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 484896500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000383 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.321993 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015707 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015707 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31074.362606 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31161.849711 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31103.040308 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31074.362606 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31104.407417 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31074.362606 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31104.407417 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 721 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 355 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14534 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 14534 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 721 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 14889 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 15610 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 721 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 14889 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 15610 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22414000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11074500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 33488500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 452032500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 452032500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22414000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 463107000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 485521000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22414000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 463107000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 485521000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000393 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.325962 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.378641 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31195.774648 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31101.726985 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 15:51:19
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:03:02
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 54240666000 # Number of ticks simulated
final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2969105 # Simulator instruction rate (inst/s)
-host_op_rate 2990423 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1777502999 # Simulator tick rate (ticks/s)
-host_mem_usage 349280 # Number of bytes of host memory used
-host_seconds 30.52 # Real time elapsed on the host
+host_inst_rate 2795699 # Simulator instruction rate (inst/s)
+host_op_rate 2815772 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1673691127 # Simulator tick rate (ticks/s)
+host_mem_usage 346432 # Number of bytes of host memory used
+host_seconds 32.41 # Real time elapsed on the host
sim_insts 90602415 # Number of instructions simulated
sim_ops 91252969 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 521339715 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_func_calls 96832 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 15564339 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 15548926 # number of instructions that are conditional controls
system.cpu.num_int_insts 72525682 # number of integer instructions
system.cpu.num_fp_insts 48 # number of float instructions
system.cpu.num_int_register_reads 396912516 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 15:51:58
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:03:45
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 148086239000 # Number of ticks simulated
final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1772363 # Simulator instruction rate (inst/s)
-host_op_rate 1785070 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2897675173 # Simulator tick rate (ticks/s)
-host_mem_usage 358192 # Number of bytes of host memory used
-host_seconds 51.11 # Real time elapsed on the host
+host_inst_rate 1876733 # Simulator instruction rate (inst/s)
+host_op_rate 1890189 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3068313156 # Simulator tick rate (ticks/s)
+host_mem_usage 355600 # Number of bytes of host memory used
+host_seconds 48.26 # Real time elapsed on the host
sim_insts 90576869 # Number of instructions simulated
sim_ops 91226321 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 986112 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_func_calls 96832 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 15564339 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 15548926 # number of instructions that are conditional controls
system.cpu.num_int_insts 72525682 # number of integer instructions
system.cpu.num_fp_insts 48 # number of float instructions
system.cpu.num_int_register_reads 464563396 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:18:33
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:04:44
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 234107886500 because target called exit()
+Exiting @ tick 233057542500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.234108 # Number of seconds simulated
-sim_ticks 234107886500 # Number of ticks simulated
-final_tick 234107886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.233058 # Number of seconds simulated
+sim_ticks 233057542500 # Number of ticks simulated
+final_tick 233057542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 148403 # Simulator instruction rate (inst/s)
-host_op_rate 167177 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 68261843 # Simulator tick rate (ticks/s)
-host_mem_usage 232040 # Number of bytes of host memory used
-host_seconds 3429.56 # Real time elapsed on the host
-sim_insts 508954871 # Number of instructions simulated
-sim_ops 573341432 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 15193216 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 241280 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 10938560 # Number of bytes written to this memory
-system.physmem.num_reads 237394 # Number of read requests responded to by this memory
-system.physmem.num_writes 170915 # Number of write requests responded to by this memory
+host_inst_rate 173099 # Simulator instruction rate (inst/s)
+host_op_rate 194997 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 79264326 # Simulator tick rate (ticks/s)
+host_mem_usage 229800 # Number of bytes of host memory used
+host_seconds 2940.26 # Real time elapsed on the host
+sim_insts 508954936 # Number of instructions simulated
+sim_ops 573341497 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 15214144 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 246208 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 10947904 # Number of bytes written to this memory
+system.physmem.num_reads 237721 # Number of read requests responded to by this memory
+system.physmem.num_writes 171061 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 64898352 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 1030636 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 46724440 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 111622792 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 65280633 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1056426 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 46975111 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 112255745 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 468215774 # number of cpu cycles simulated
+system.cpu.numCycles 466115086 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 200061766 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 161279268 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 13261114 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 110371027 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 98350021 # Number of BTB hits
+system.cpu.BPredUnit.lookups 200399400 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 157559949 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 13227368 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 107557824 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 98829929 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 10012114 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 2451761 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 136559610 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 898175750 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 200061766 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 108362135 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 197576941 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 54094157 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 91756620 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 80 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 71734 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 126283016 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 3812130 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 464400798 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.257289 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.102621 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 10084316 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 2451057 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 137234241 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 896616118 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 200399400 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 108914245 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 197636410 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 54052361 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 88992455 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1657 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 126860220 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 3882835 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 462293499 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.263975 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.101557 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 266835612 57.46% 57.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 16224757 3.49% 60.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 21301662 4.59% 65.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 22971866 4.95% 70.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 24200733 5.21% 75.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 13160700 2.83% 78.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 13387272 2.88% 81.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 12932496 2.78% 84.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 73385700 15.80% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 264670388 57.25% 57.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 16165090 3.50% 60.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 21531844 4.66% 65.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 22983454 4.97% 70.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 24508471 5.30% 75.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 13134616 2.84% 78.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 13371052 2.89% 81.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 12920313 2.79% 84.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 73008271 15.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 464400798 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.427285 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.918295 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 151819691 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 87315779 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 182356495 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 4679019 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 38229814 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 32058950 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 208727 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 978247672 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 304018 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 38229814 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 165098123 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 6680773 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 67210378 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 173611976 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 13569734 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 900335199 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1400 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2808611 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 7742666 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 62 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 1050683608 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3921835451 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3921830870 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4581 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 672199728 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 378483880 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 6257639 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 6252483 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 74230305 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 187204403 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 74981295 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 17030714 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 11234948 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 805916100 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 7086662 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 700681614 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1544151 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 236754435 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 596849341 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 3208414 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 464400798 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.508786 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.706470 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 462293499 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.429935 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.923594 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 152295850 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 84600682 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 182545472 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 4580461 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 38271034 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 32275508 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 160463 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 977106792 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 311018 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 38271034 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 165689191 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 6700759 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 64642468 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 173582675 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 13407372 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 899108485 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1442 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2810546 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 7739563 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 106 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 1049429059 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3915911188 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3915906253 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 4935 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 672199832 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 377229227 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 5987863 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 5982547 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 72814411 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 187298810 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 75062120 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 17028922 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 10874751 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 806565254 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 6815793 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 700720615 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1613210 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 237113606 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 598814504 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 3094720 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 462293499 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.515748 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.710183 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 194454987 41.87% 41.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 75651609 16.29% 58.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 69485384 14.96% 73.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 61139015 13.17% 86.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 35296693 7.60% 93.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15466096 3.33% 97.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 7603561 1.64% 98.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3924050 0.84% 99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1379403 0.30% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 192936549 41.73% 41.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 75135766 16.25% 57.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 69228865 14.98% 72.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 61089071 13.21% 86.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 35380643 7.65% 93.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15554118 3.36% 97.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 7568076 1.64% 98.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 4045000 0.87% 99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1355411 0.29% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 464400798 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 462293499 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 453814 4.63% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 6693711 68.30% 72.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2653315 27.07% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 467117 4.69% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 6749256 67.80% 72.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2738977 27.51% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 472302081 67.41% 67.41% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 386521 0.06% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 472287152 67.40% 67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 386091 0.06% 67.46% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 170 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 198 0.00% 67.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 162598638 23.21% 90.67% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 65394201 9.33% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 162565842 23.20% 90.66% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 65481329 9.34% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 700681614 # Type of FU issued
-system.cpu.iq.rate 1.496493 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 9800840 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.013988 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1877108639 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1049814796 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 668235184 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 378 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 790 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 700720615 # Type of FU issued
+system.cpu.iq.rate 1.503321 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 9955350 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014207 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1875302857 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 1050553482 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 668216510 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 432 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 858 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 710482264 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 190 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 9094204 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 710675747 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 218 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 9109880 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 60431419 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 43883 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 61918 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 17377390 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 60525813 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 50692 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 63405 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 17458202 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 20851 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 399 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 20818 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 376 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 38229814 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2886721 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 175953 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 821878596 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 9525062 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 187204403 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 74981295 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 5597916 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 86243 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 8756 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 61918 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 10539331 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 7737636 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 18276967 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 681941706 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 155293366 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 18739908 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 38271034 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2890868 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 175492 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 822161545 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 8144996 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 187298810 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 75062120 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 5327019 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 85808 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 8514 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 63405 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 10568276 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 7702731 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 18271007 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 681861282 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 155223597 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 18859333 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 8875834 # number of nop insts executed
-system.cpu.iew.exec_refs 219203468 # number of memory reference insts executed
-system.cpu.iew.exec_branches 142018558 # Number of branches executed
-system.cpu.iew.exec_stores 63910102 # Number of stores executed
-system.cpu.iew.exec_rate 1.456469 # Inst execution rate
-system.cpu.iew.wb_sent 673034239 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 668235200 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 381399199 # num instructions producing a value
-system.cpu.iew.wb_consumers 655303832 # num instructions consuming a value
+system.cpu.iew.exec_nop 8780498 # number of nop insts executed
+system.cpu.iew.exec_refs 219185272 # number of memory reference insts executed
+system.cpu.iew.exec_branches 141958281 # Number of branches executed
+system.cpu.iew.exec_stores 63961675 # Number of stores executed
+system.cpu.iew.exec_rate 1.462860 # Inst execution rate
+system.cpu.iew.wb_sent 673014173 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 668216526 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 381765084 # num instructions producing a value
+system.cpu.iew.wb_consumers 656387982 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.427195 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.582019 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.433587 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.581615 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 510298755 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 574685316 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 247211019 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 3878248 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 15402240 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 426170985 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.348485 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.065618 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 510298820 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 574685381 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 247493136 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 3721073 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 15415046 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 424022466 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.355318 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.071268 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 207821757 48.76% 48.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 103278684 24.23% 73.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 40154361 9.42% 82.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 19502589 4.58% 87.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 17446456 4.09% 91.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7236627 1.70% 92.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 7721645 1.81% 94.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3779614 0.89% 95.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 19229252 4.51% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 206316988 48.66% 48.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 102533575 24.18% 72.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 40145036 9.47% 82.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 19513900 4.60% 86.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 17437160 4.11% 91.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7239208 1.71% 92.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 7753458 1.83% 94.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3810522 0.90% 95.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 19272619 4.55% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 426170985 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 510298755 # Number of instructions committed
-system.cpu.commit.committedOps 574685316 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 424022466 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 510298820 # Number of instructions committed
+system.cpu.commit.committedOps 574685381 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 184376889 # Number of memory references committed
-system.cpu.commit.loads 126772984 # Number of loads committed
+system.cpu.commit.refs 184376915 # Number of memory references committed
+system.cpu.commit.loads 126772997 # Number of loads committed
system.cpu.commit.membars 1488542 # Number of memory barriers committed
-system.cpu.commit.branches 120192169 # Number of branches committed
+system.cpu.commit.branches 120192182 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 473701413 # Number of committed integer instructions.
+system.cpu.commit.int_insts 473701465 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 19229252 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 19272619 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1228830930 # The number of ROB reads
-system.cpu.rob.rob_writes 1682168121 # The number of ROB writes
-system.cpu.timesIdled 98147 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 3814976 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 508954871 # Number of Instructions Simulated
-system.cpu.committedOps 573341432 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 508954871 # Number of Instructions Simulated
-system.cpu.cpi 0.919955 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.919955 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.087009 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.087009 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3163894948 # number of integer regfile reads
-system.cpu.int_regfile_writes 777442018 # number of integer regfile writes
+system.cpu.rob.rob_reads 1226921226 # The number of ROB reads
+system.cpu.rob.rob_writes 1682775882 # The number of ROB writes
+system.cpu.timesIdled 98525 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 3821587 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 508954936 # Number of Instructions Simulated
+system.cpu.committedOps 573341497 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 508954936 # Number of Instructions Simulated
+system.cpu.cpi 0.915828 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.915828 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.091908 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.091908 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3163594515 # number of integer regfile reads
+system.cpu.int_regfile_writes 777373809 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 1131493621 # number of misc regfile reads
-system.cpu.misc_regfile_writes 4463940 # number of misc regfile writes
-system.cpu.icache.replacements 16054 # number of replacements
-system.cpu.icache.tagsinuse 1101.947975 # Cycle average of tags in use
-system.cpu.icache.total_refs 126263236 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 17918 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 7046.725974 # Average number of references to valid blocks.
+system.cpu.misc_regfile_reads 1130092901 # number of misc regfile reads
+system.cpu.misc_regfile_writes 4463966 # number of misc regfile writes
+system.cpu.icache.replacements 16105 # number of replacements
+system.cpu.icache.tagsinuse 1117.727093 # Cycle average of tags in use
+system.cpu.icache.total_refs 126840323 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 17981 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 7054.130638 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1101.947975 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.538061 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.538061 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 126263236 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 126263236 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 126263236 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 126263236 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 126263236 # number of overall hits
-system.cpu.icache.overall_hits::total 126263236 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 19780 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 19780 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 19780 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 19780 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 19780 # number of overall misses
-system.cpu.icache.overall_misses::total 19780 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 264112500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 264112500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 264112500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 264112500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 264112500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 264112500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 126283016 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 126283016 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 126283016 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 126283016 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 126283016 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 126283016 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 1117.727093 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.545765 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.545765 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 126840329 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 126840329 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 126840329 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 126840329 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 126840329 # number of overall hits
+system.cpu.icache.overall_hits::total 126840329 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 19891 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 19891 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 19891 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 19891 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 19891 # number of overall misses
+system.cpu.icache.overall_misses::total 19891 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 267894500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 267894500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 267894500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 267894500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 267894500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 267894500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 126860220 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 126860220 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 126860220 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 126860220 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 126860220 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 126860220 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000157 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000157 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000157 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13352.502528 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13352.502528 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13352.502528 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13468.126288 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1738 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 1738 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 1738 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 1738 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 1738 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 1738 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18042 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 18042 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 18042 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 18042 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 18042 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 18042 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168794500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 168794500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168794500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 168794500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168794500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 168794500 # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks 1 # number of writebacks
+system.cpu.icache.writebacks::total 1 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1759 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 1759 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 1759 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 1759 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 1759 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 1759 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18132 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 18132 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 18132 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 18132 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 18132 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 18132 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171640500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 171640500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171640500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 171640500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171640500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 171640500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9355.642390 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9355.642390 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9355.642390 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9466.164792 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1204439 # number of replacements
-system.cpu.dcache.tagsinuse 4053.213241 # Cycle average of tags in use
-system.cpu.dcache.total_refs 197393966 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1208535 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 163.333264 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 5508997000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4053.213241 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.989554 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.989554 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 140143872 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 140143872 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 52777243 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 52777243 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 2240634 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 2240634 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 2231969 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 2231969 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 192921115 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 192921115 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 192921115 # number of overall hits
-system.cpu.dcache.overall_hits::total 192921115 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1321702 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1321702 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1462063 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1462063 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 79 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 79 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 2783765 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2783765 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2783765 # number of overall misses
-system.cpu.dcache.overall_misses::total 2783765 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 15361891000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 15361891000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 24945206993 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 24945206993 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 848000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 848000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 40307097993 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 40307097993 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 40307097993 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 40307097993 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 141465574 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 141465574 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements 1204809 # number of replacements
+system.cpu.dcache.tagsinuse 4052.906677 # Cycle average of tags in use
+system.cpu.dcache.total_refs 197317737 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1208905 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 163.220217 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 5518270000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4052.906677 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.989479 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.989479 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 140063979 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 140063979 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 52782968 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 52782968 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 2238489 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 2238489 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 2231982 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 2231982 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 192846947 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 192846947 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 192846947 # number of overall hits
+system.cpu.dcache.overall_hits::total 192846947 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1318830 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1318830 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1456338 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1456338 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 78 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 78 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 2775168 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2775168 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2775168 # number of overall misses
+system.cpu.dcache.overall_misses::total 2775168 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 15287682000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 15287682000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 25164058992 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 25164058992 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 845500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 845500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 40451740992 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 40451740992 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 40451740992 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 40451740992 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 141382809 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 141382809 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2240713 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 2240713 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231969 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 2231969 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 195704880 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 195704880 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 195704880 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 195704880 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009343 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026956 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2238567 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 2238567 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231982 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 2231982 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 195622115 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 195622115 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 195622115 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 195622115 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009328 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026850 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000035 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.014224 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.014224 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11622.809832 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17061.649869 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10734.177215 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14479.346494 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14479.346494 # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.014186 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.014186 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11591.851869 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17278.996354 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10839.743590 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 557000 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 602000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 92 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 6054.347826 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 6543.478261 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1073316 # number of writebacks
-system.cpu.dcache.writebacks::total 1073316 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 452437 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 452437 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1122680 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1122680 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 79 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 79 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1575117 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1575117 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1575117 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1575117 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 869265 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 869265 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 339383 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 339383 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1208648 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1208648 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1208648 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1208648 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6267661500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 6267661500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4319283499 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4319283499 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10586944999 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10586944999 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10586944999 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10586944999 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006145 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006257 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006176 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006176 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7210.300081 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12726.870524 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8759.328604 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8759.328604 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 1073322 # number of writebacks
+system.cpu.dcache.writebacks::total 1073322 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 451055 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 451055 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1115056 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1115056 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 78 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 78 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1566111 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1566111 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1566111 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1566111 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 867775 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 867775 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 341282 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 341282 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1209057 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1209057 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1209057 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1209057 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6208585000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 6208585000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4381340497 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4381340497 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10589925497 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10589925497 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10589925497 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10589925497 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006138 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006292 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7154.602287 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12837.889185 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 218164 # number of replacements
-system.cpu.l2cache.tagsinuse 21000.033728 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1558335 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 238544 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 6.532694 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 171274972000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 13326.233145 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 198.028961 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 7475.771622 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.406684 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.006043 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.228142 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.640870 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 14176 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 742295 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 756471 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1073316 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1073316 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 79 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 79 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 232581 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 232581 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 14176 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 974876 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 989052 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 14176 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 974876 # number of overall hits
-system.cpu.l2cache.overall_hits::total 989052 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3773 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 126291 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 130064 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 30 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 30 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 107358 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 107358 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3773 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 233649 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 237422 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3773 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 233649 # number of overall misses
-system.cpu.l2cache.overall_misses::total 237422 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 129366000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4319010500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 4448376500 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 170500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 170500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3675900000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 3675900000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 129366000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 7994910500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 8124276500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 129366000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 7994910500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 8124276500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 17949 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 868586 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 886535 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 1073316 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 1073316 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 109 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 109 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 339939 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 339939 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 17949 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1208525 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1226474 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 17949 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1208525 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1226474 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.210207 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.145398 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.275229 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.315815 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.210207 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.193334 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.210207 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.193334 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34287.304532 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34198.877988 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 5683.333333 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34239.646789 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.304532 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34217.610604 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.304532 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34217.610604 # average overall miss latency
+system.cpu.l2cache.replacements 218501 # number of replacements
+system.cpu.l2cache.tagsinuse 20930.395337 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1557466 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 238907 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 6.519131 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 170551572000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 13694.941090 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 198.526640 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 7036.927606 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.417936 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.006059 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.214750 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.638745 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 14165 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 742446 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 756611 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 1073323 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 1073323 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 110 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 110 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 232553 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 232553 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 14165 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 974999 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 989164 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 14165 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 974999 # number of overall hits
+system.cpu.l2cache.overall_hits::total 989164 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3852 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 124612 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 128464 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 33 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 33 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 109285 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 109285 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3852 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 233897 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 237749 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3852 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 233897 # number of overall misses
+system.cpu.l2cache.overall_misses::total 237749 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132071500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4261496000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 4393567500 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 205000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 205000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3742208000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 3742208000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 132071500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 8003704000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 8135775500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 132071500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 8003704000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 8135775500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 18017 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 867058 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 885075 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1073323 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1073323 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 143 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 143 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 341838 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 341838 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 18017 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1208896 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1226913 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 18017 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1208896 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1226913 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.213798 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.143718 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.319698 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.213798 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.193480 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.213798 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.193480 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34286.474559 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34198.118961 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6212.121212 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34242.649952 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34286.474559 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34218.925424 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34286.474559 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34218.925424 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 170915 # number of writebacks
-system.cpu.l2cache.writebacks::total 170915 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks 171061 # number of writebacks
+system.cpu.l2cache.writebacks::total 171061 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3770 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 126267 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 130037 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 30 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 30 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 107358 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 107358 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3770 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 233625 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 237395 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3770 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 233625 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 237395 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117154500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3918910500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4036065000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 933000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 933000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3328751000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3328751000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117154500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7247661500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 7364816000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117154500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7247661500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 7364816000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.210040 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.145371 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.275229 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.315815 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.210040 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193314 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.210040 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193314 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31075.464191 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.696049 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31100 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31006.082453 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31075.464191 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31022.628143 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31075.464191 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31022.628143 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3847 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 124590 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 128437 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 109285 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 109285 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3847 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 233875 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 237722 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3847 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 233875 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 237722 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 119582500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3866885000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3986467500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1024500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1024500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3388776000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3388776000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 119582500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7255661000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 7375243500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 119582500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7255661000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 7375243500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.143693 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.319698 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31084.611385 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.880970 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31045.454545 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.610514 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 15:54:26
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:09:21
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 290498972000 # Number of ticks simulated
final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3161801 # Simulator instruction rate (inst/s)
-host_op_rate 3563665 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1813132581 # Simulator tick rate (ticks/s)
-host_mem_usage 219872 # Number of bytes of host memory used
-host_seconds 160.22 # Real time elapsed on the host
+host_inst_rate 2826052 # Simulator instruction rate (inst/s)
+host_op_rate 3185244 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1620598119 # Simulator tick rate (ticks/s)
+host_mem_usage 217292 # Number of bytes of host memory used
+host_seconds 179.25 # Real time elapsed on the host
sim_insts 506581615 # Number of instructions simulated
sim_ops 570968176 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 2489298238 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 98480815 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 94894805 # number of instructions that are conditional controls
system.cpu.num_int_insts 470727703 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2465023721 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:18:46
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:11:24
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 722234364000 # Number of ticks simulated
final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1812748 # Simulator instruction rate (inst/s)
-host_op_rate 2042661 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2592600297 # Simulator tick rate (ticks/s)
-host_mem_usage 228776 # Number of bytes of host memory used
-host_seconds 278.58 # Real time elapsed on the host
+host_inst_rate 1807546 # Simulator instruction rate (inst/s)
+host_op_rate 2036799 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2585159889 # Simulator tick rate (ticks/s)
+host_mem_usage 226208 # Number of bytes of host memory used
+host_seconds 279.38 # Real time elapsed on the host
sim_insts 504986861 # Number of instructions simulated
sim_ops 569034848 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 14797056 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 98480815 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 94894805 # number of instructions that are conditional controls
system.cpu.num_int_insts 470727703 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:18:58
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:12:32
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
-OO-style eon Time= 0.090000
-Exiting @ tick 99661890000 because target called exit()
+OO-style eon Time= 0.070000
+Exiting @ tick 71774859500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.099662 # Number of seconds simulated
-sim_ticks 99661890000 # Number of ticks simulated
-final_tick 99661890000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.071775 # Number of seconds simulated
+sim_ticks 71774859500 # Number of ticks simulated
+final_tick 71774859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 162959 # Simulator instruction rate (inst/s)
-host_op_rate 208335 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 59481796 # Simulator tick rate (ticks/s)
-host_mem_usage 235924 # Number of bytes of host memory used
-host_seconds 1675.50 # Real time elapsed on the host
-sim_insts 273037886 # Number of instructions simulated
-sim_ops 349065611 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 467712 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 196352 # Number of instructions bytes read from this memory
+host_inst_rate 200202 # Simulator instruction rate (inst/s)
+host_op_rate 255946 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 52626024 # Simulator tick rate (ticks/s)
+host_mem_usage 233120 # Number of bytes of host memory used
+host_seconds 1363.87 # Real time elapsed on the host
+sim_insts 273048474 # Number of instructions simulated
+sim_ops 349076199 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 472896 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 199168 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 7308 # Number of read requests responded to by this memory
+system.physmem.num_reads 7389 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 4692987 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 1970181 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 4692987 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 6588602 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 2774899 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 6588602 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
-system.cpu.numCycles 199323781 # number of cpu cycles simulated
+system.cpu.numCycles 143549720 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 36425277 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 21814093 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 2195714 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 21857400 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 17699652 # Number of BTB hits
+system.cpu.BPredUnit.lookups 37175542 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 22262323 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 2214096 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 22505770 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 18082192 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 6983514 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 50540 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 40843667 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 325977974 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 36425277 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 24683166 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 73206871 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 8096294 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 79308750 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 3272 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 39251627 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 692341 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 199214408 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.104516 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.205209 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 7072101 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 52600 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 41561697 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 332366381 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 37175542 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 25154293 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 74569841 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 8920940 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 20643175 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 4492 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 39951299 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 710527 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 143433675 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.978110 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.454958 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 126685996 63.59% 63.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 7392332 3.71% 67.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 5861965 2.94% 70.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 6253075 3.14% 73.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4927164 2.47% 75.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4136176 2.08% 77.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3211031 1.61% 79.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 4254661 2.14% 81.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 36492008 18.32% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 69560380 48.50% 48.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 7529870 5.25% 53.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 5927266 4.13% 57.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 6353418 4.43% 62.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 5053258 3.52% 65.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4245115 2.96% 68.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 3249040 2.27% 71.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 4338891 3.03% 74.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 37176437 25.92% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 199214408 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.182744 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.635419 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 48091997 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 74157554 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 67325954 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3856814 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 5782089 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 7547074 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 69910 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 411121431 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 208451 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 5782089 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 55063328 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1232045 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 57746804 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 64402683 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 14987459 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 399689928 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 40994 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 8558988 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 23 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 436461452 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2357603268 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1290965650 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1066637618 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 384568055 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 51893397 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 3989281 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 4086766 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 48885430 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 104583194 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 92996995 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2832218 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 4219793 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 383881743 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 3901955 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 374859266 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1372272 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 37676176 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 103140014 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 346328 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 199214408 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.881688 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.014261 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 143433675 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.258973 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.315340 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 48398038 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 15922899 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 70106313 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 2422163 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 6584262 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 7647961 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 70686 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 419107715 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 208401 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 6584262 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 54237445 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1551128 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 362766 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 66624532 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 14073542 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 408263314 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1648402 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 10108765 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 752 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 447190592 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2407780645 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1318183800 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1089596845 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 384584999 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 62605593 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 23936 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 23899 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 35817763 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 106133186 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 93562284 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 4587440 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 5646194 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 394242574 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 33887 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 379407553 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1341475 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 44167400 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 116755410 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 9405 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 143433675 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.645178 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.047092 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 75091477 37.69% 37.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 33471491 16.80% 54.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 23546496 11.82% 66.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 17816115 8.94% 75.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 22176914 11.13% 86.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15007629 7.53% 93.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8468208 4.25% 98.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 2797235 1.40% 99.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 838843 0.42% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 29947758 20.88% 20.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 20633542 14.39% 35.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 21077069 14.69% 49.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 18246072 12.72% 62.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 24216587 16.88% 79.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 16050569 11.19% 90.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 9012327 6.28% 97.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3309506 2.31% 99.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 940245 0.66% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 199214408 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 143433675 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 3057 0.02% 0.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5025 0.03% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 40437 0.24% 0.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 3591 0.02% 0.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 364 0.00% 0.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 63031 0.37% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 1376 0.01% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 149950 0.89% 1.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8836509 52.25% 53.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 7809442 46.17% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 9527 0.05% 0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4696 0.03% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 47773 0.27% 0.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 7824 0.04% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 381 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 194196 1.08% 1.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 4065 0.02% 1.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 241389 1.34% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 9461548 52.57% 55.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 8027461 44.60% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 127218722 33.94% 33.94% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2147662 0.57% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 4 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 1 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 6752754 1.80% 36.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 8445549 2.25% 38.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 3419085 0.91% 39.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1579460 0.42% 39.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 20849528 5.56% 45.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 7172342 1.91% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 7118324 1.90% 49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 101990541 27.21% 76.53% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 87990007 23.47% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 129140993 34.04% 34.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2178888 0.57% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 6841737 1.80% 36.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 8706483 2.29% 38.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 3462240 0.91% 39.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1609824 0.42% 40.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 21270001 5.61% 45.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 7182346 1.89% 47.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 7142588 1.88% 49.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.47% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 102963295 27.14% 76.61% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 88733868 23.39% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 374859266 # Type of FU issued
-system.cpu.iq.rate 1.880655 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 16912785 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.045118 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 719593529 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 296504031 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 250306667 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 247624468 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 128964922 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 117586691 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 264413654 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 127358397 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 8761278 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 379407553 # Type of FU issued
+system.cpu.iq.rate 2.643039 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 17998863 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.047439 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 670841771 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 305961612 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 253223434 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 250747348 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 132496015 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 118776381 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 268120952 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 129285464 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 10792483 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 9934214 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 114912 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 9298 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 10621174 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 11482088 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 116027 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 13932 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 11184344 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 12907 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 180 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 9709 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 181 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 5782089 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 25749 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2296 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 387833269 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1480942 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 104583194 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 92996995 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 3890825 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 126 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 225 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 9298 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1748842 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 550283 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 2299125 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 370161123 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 100475616 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 4698143 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 6584262 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 34186 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1479 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 394326849 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1347232 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 106133186 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 93562284 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 22722 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 192 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 169 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 13932 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1780753 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 562062 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 2342815 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 374477920 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 101438803 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 4929633 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 49571 # number of nop insts executed
-system.cpu.iew.exec_refs 187121240 # number of memory reference insts executed
-system.cpu.iew.exec_branches 32102790 # Number of branches executed
-system.cpu.iew.exec_stores 86645624 # Number of stores executed
-system.cpu.iew.exec_rate 1.857085 # Inst execution rate
-system.cpu.iew.wb_sent 368581318 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 367893358 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 175547849 # num instructions producing a value
-system.cpu.iew.wb_consumers 345820695 # num instructions consuming a value
+system.cpu.iew.exec_nop 50388 # number of nop insts executed
+system.cpu.iew.exec_refs 188856020 # number of memory reference insts executed
+system.cpu.iew.exec_branches 32491949 # Number of branches executed
+system.cpu.iew.exec_stores 87417217 # Number of stores executed
+system.cpu.iew.exec_rate 2.608698 # Inst execution rate
+system.cpu.iew.wb_sent 372876985 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 371999815 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 185166823 # num instructions producing a value
+system.cpu.iew.wb_consumers 368327153 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.845707 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.507627 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.591435 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.502724 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 273038498 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 349066223 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 38767213 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 3555627 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2167826 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 193432320 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.804591 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.360078 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 273049086 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 349076811 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 45250302 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 24482 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 2186131 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 136849414 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.550810 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.650371 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 83176077 43.00% 43.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 39065690 20.20% 63.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 17086597 8.83% 72.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 13450710 6.95% 78.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 14290443 7.39% 86.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7491330 3.87% 90.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 3442946 1.78% 92.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3229105 1.67% 93.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 12199422 6.31% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 39364225 28.76% 28.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 29162916 21.31% 50.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13605145 9.94% 60.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 11228015 8.20% 68.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 13810148 10.09% 78.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7236976 5.29% 83.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 4020101 2.94% 86.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3901622 2.85% 89.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 14520266 10.61% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 193432320 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 273038498 # Number of instructions committed
-system.cpu.commit.committedOps 349066223 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 136849414 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 273049086 # Number of instructions committed
+system.cpu.commit.committedOps 349076811 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 177024801 # Number of memory references committed
-system.cpu.commit.loads 94648980 # Number of loads committed
+system.cpu.commit.refs 177029038 # Number of memory references committed
+system.cpu.commit.loads 94651098 # Number of loads committed
system.cpu.commit.membars 11033 # Number of memory barriers committed
-system.cpu.commit.branches 30521876 # Number of branches committed
+system.cpu.commit.branches 30523993 # Number of branches committed
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 279585540 # Number of committed integer instructions.
+system.cpu.commit.int_insts 279594011 # Number of committed integer instructions.
system.cpu.commit.function_calls 6225112 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 12199422 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 14520266 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 569063811 # The number of ROB reads
-system.cpu.rob.rob_writes 781450888 # The number of ROB writes
-system.cpu.timesIdled 2411 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 109373 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 273037886 # Number of Instructions Simulated
-system.cpu.committedOps 349065611 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 273037886 # Number of Instructions Simulated
-system.cpu.cpi 0.730022 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.730022 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.369821 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.369821 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1768986911 # number of integer regfile reads
-system.cpu.int_regfile_writes 233848403 # number of integer regfile writes
-system.cpu.fp_regfile_reads 187568002 # number of floating regfile reads
-system.cpu.fp_regfile_writes 132321236 # number of floating regfile writes
-system.cpu.misc_regfile_reads 981099777 # number of misc regfile reads
-system.cpu.misc_regfile_writes 34422237 # number of misc regfile writes
-system.cpu.icache.replacements 14037 # number of replacements
-system.cpu.icache.tagsinuse 1859.121830 # Cycle average of tags in use
-system.cpu.icache.total_refs 39234784 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 15929 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 2463.104024 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 516653738 # The number of ROB reads
+system.cpu.rob.rob_writes 795243409 # The number of ROB writes
+system.cpu.timesIdled 2720 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 116045 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 273048474 # Number of Instructions Simulated
+system.cpu.committedOps 349076199 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 273048474 # Number of Instructions Simulated
+system.cpu.cpi 0.525730 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.525730 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.902118 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.902118 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1788157543 # number of integer regfile reads
+system.cpu.int_regfile_writes 236964047 # number of integer regfile writes
+system.cpu.fp_regfile_reads 189767378 # number of floating regfile reads
+system.cpu.fp_regfile_writes 133494852 # number of floating regfile writes
+system.cpu.misc_regfile_reads 995239791 # number of misc regfile reads
+system.cpu.misc_regfile_writes 34426479 # number of misc regfile writes
+system.cpu.icache.replacements 14190 # number of replacements
+system.cpu.icache.tagsinuse 1864.933817 # Cycle average of tags in use
+system.cpu.icache.total_refs 39934285 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 16092 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 2481.623478 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1859.121830 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.907774 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.907774 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 39234786 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 39234786 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 39234786 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 39234786 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 39234786 # number of overall hits
-system.cpu.icache.overall_hits::total 39234786 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 16841 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 16841 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 16841 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 16841 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 16841 # number of overall misses
-system.cpu.icache.overall_misses::total 16841 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 208423500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 208423500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 208423500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 208423500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 208423500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 208423500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 39251627 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 39251627 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 39251627 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 39251627 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 39251627 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 39251627 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000429 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000429 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000429 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12375.957485 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 12375.957485 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 12375.957485 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1864.933817 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.910612 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.910612 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 39934285 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 39934285 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 39934285 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 39934285 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 39934285 # number of overall hits
+system.cpu.icache.overall_hits::total 39934285 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 17014 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 17014 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 17014 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 17014 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 17014 # number of overall misses
+system.cpu.icache.overall_misses::total 17014 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 211050500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 211050500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 211050500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 211050500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 211050500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 211050500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 39951299 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 39951299 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 39951299 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 39951299 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 39951299 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 39951299 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000426 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000426 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000426 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12404.519807 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 888 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 888 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 888 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 888 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 888 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 888 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15953 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 15953 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 15953 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 15953 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 15953 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 15953 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 137773000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 137773000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 137773000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 137773000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 137773000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 137773000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8636.181283 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8636.181283 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8636.181283 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 900 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 900 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 900 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 900 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 900 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 900 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16114 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 16114 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 16114 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 16114 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 16114 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 16114 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 139714000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 139714000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 139714000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 139714000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 139714000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 139714000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8670.348765 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1416 # number of replacements
-system.cpu.dcache.tagsinuse 3097.112853 # Cycle average of tags in use
-system.cpu.dcache.total_refs 173600890 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 4598 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 37755.739452 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 1427 # number of replacements
+system.cpu.dcache.tagsinuse 3127.647604 # Cycle average of tags in use
+system.cpu.dcache.total_refs 172501472 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 4641 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 37169.030812 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3097.112853 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.756131 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.756131 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 91544700 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 91544700 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 82033348 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 82033348 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 11669 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 11669 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 11136 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 11136 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 173578048 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 173578048 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 173578048 # number of overall hits
-system.cpu.dcache.overall_hits::total 173578048 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 3368 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 3368 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 19314 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 19314 # number of WriteReq misses
+system.cpu.dcache.occ_blocks::cpu.data 3127.647604 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.763586 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.763586 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 90441052 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 90441052 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 82033132 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 82033132 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 14008 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 14008 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 13257 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 13257 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 172474184 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 172474184 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 172474184 # number of overall hits
+system.cpu.dcache.overall_hits::total 172474184 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 3598 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 3598 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 19528 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 19528 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 22682 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 22682 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 22682 # number of overall misses
-system.cpu.dcache.overall_misses::total 22682 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 110168000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 110168000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 637892000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 637892000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 23126 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 23126 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 23126 # number of overall misses
+system.cpu.dcache.overall_misses::total 23126 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 115634000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 115634000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 650274000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 650274000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 76000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 748060000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 748060000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 748060000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 748060000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 91548068 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 91548068 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 82052662 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 82052662 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11671 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 11671 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 11136 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 11136 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 173600730 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 173600730 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 173600730 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 173600730 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000037 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000235 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000171 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000131 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000131 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32710.213777 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33027.441234 # average WriteReq miss latency
+system.cpu.dcache.demand_miss_latency::cpu.data 765908000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 765908000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 765908000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 765908000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 90444650 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 90444650 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 14010 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 14010 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 13257 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 13257 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 172497310 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 172497310 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 172497310 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 172497310 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000040 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000238 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000143 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32138.410228 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33299.569848 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32980.336831 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32980.336831 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 317500 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 315000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 22678.571429 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 24230.769231 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1038 # number of writebacks
system.cpu.dcache.writebacks::total 1038 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1605 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1605 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16455 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 16455 # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1792 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 1792 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16671 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 16671 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 18060 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 18060 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 18060 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 18060 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1763 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1763 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2859 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 2859 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4622 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4622 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4622 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4622 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53565000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 53565000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101664500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 101664500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 155229500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 155229500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 155229500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 155229500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data 18463 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 18463 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 18463 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 18463 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1806 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1806 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2857 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 2857 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 4663 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 4663 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 4663 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 4663 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 54896500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 54896500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101557000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 101557000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 156453500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 156453500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 156453500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 156453500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30382.870108 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35559.461350 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33584.919948 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33584.919948 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30396.733112 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35546.727336 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 62 # number of replacements
-system.cpu.l2cache.tagsinuse 3962.463851 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 13233 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 5422 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 2.440612 # Average number of references to valid blocks.
+system.cpu.l2cache.replacements 69 # number of replacements
+system.cpu.l2cache.tagsinuse 4034.301662 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 13357 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 5499 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.428987 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 380.682257 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 2812.020473 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 769.761121 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.011618 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.085816 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.023491 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.120925 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 12854 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 293 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 13147 # number of ReadReq hits
+system.cpu.l2cache.occ_blocks::writebacks 380.580872 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 2851.587465 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 802.133324 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.011614 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.087024 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.024479 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.123117 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 12970 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 298 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 13268 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1038 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1038 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 18 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 18 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 12854 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 311 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 13165 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 12854 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 311 # number of overall hits
-system.cpu.l2cache.overall_hits::total 13165 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3075 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 1470 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 4545 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 24 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 24 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 2817 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 2817 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3075 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 4287 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 7362 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3075 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 4287 # number of overall misses
-system.cpu.l2cache.overall_misses::total 7362 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 105351500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50523000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 155874500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 97095500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 97095500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 105351500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 147618500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 252970000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 105351500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 147618500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 252970000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 15929 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1763 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 17692 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 12970 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 315 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 13285 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 12970 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 315 # number of overall hits
+system.cpu.l2cache.overall_hits::total 13285 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3122 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 1507 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 4629 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 22 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 22 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 2819 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 2819 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3122 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 4326 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 7448 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3122 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 4326 # number of overall misses
+system.cpu.l2cache.overall_misses::total 7448 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 106982000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51758500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 158740500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 97188000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 97188000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 106982000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 148946500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 255928500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 106982000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 148946500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 255928500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 16092 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1805 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 17897 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1038 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1038 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 24 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 24 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 2835 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 2835 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 15929 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 4598 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 20527 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 15929 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 4598 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 20527 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.193044 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.833806 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 22 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 2836 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 2836 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 16092 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 4641 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 20733 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 16092 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 4641 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 20733 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.194009 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.834903 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993651 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.193044 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.932362 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.193044 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.932362 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34260.650407 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34369.387755 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34467.696131 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34260.650407 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34433.986471 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34260.650407 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34433.986471 # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994006 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.194009 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.932127 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.194009 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.932127 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.136451 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34345.388188 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34476.055339 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 7 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 47 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 47 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 54 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 47 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 54 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3068 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1423 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 4491 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 24 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 24 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2817 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 2817 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3068 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 4240 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 7308 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3068 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 4240 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 7308 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 95355500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44533000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 139888500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 744000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 744000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 88103500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 88103500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95355500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132636500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 227992000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95355500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132636500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 227992000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192605 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807147 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 49 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 49 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 59 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3112 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1458 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 4570 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 22 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 22 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2819 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 2819 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3112 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 4277 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 7389 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3112 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 4277 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 7389 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96743500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 45668000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 142411500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 682000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 682000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 88208000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 88208000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96743500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 133876000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 230619500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96743500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 133876000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 230619500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807756 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993651 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192605 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922140 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192605 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922140 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31080.671447 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31295.151089 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994006 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.242931 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31322.359396 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31275.647852 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31080.671447 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31282.193396 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31080.671447 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31282.193396 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31290.528556 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 15:59:35
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:16:14
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 212344048000 # Number of ticks simulated
final_tick 212344048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2182036 # Simulator instruction rate (inst/s)
-host_op_rate 2789626 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1696989772 # Simulator tick rate (ticks/s)
-host_mem_usage 224464 # Number of bytes of host memory used
-host_seconds 125.13 # Real time elapsed on the host
+host_inst_rate 1971895 # Simulator instruction rate (inst/s)
+host_op_rate 2520972 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1533561642 # Simulator tick rate (ticks/s)
+host_mem_usage 221584 # Number of bytes of host memory used
+host_seconds 138.46 # Real time elapsed on the host
sim_insts 273037671 # Number of instructions simulated
sim_ops 349065408 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 1875350709 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 279584926 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
system.cpu.num_func_calls 12433363 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 18102314 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 18087062 # number of instructions that are conditional controls
system.cpu.num_int_insts 279584926 # number of integer instructions
system.cpu.num_fp_insts 114216705 # number of float instructions
system.cpu.num_int_register_reads 1887652191 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 16:01:56
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:16:21
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 525854475000 # Number of ticks simulated
final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1224247 # Simulator instruction rate (inst/s)
-host_op_rate 1565155 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2360407719 # Simulator tick rate (ticks/s)
-host_mem_usage 233372 # Number of bytes of host memory used
-host_seconds 222.78 # Real time elapsed on the host
+host_inst_rate 1189484 # Simulator instruction rate (inst/s)
+host_op_rate 1520711 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2293381880 # Simulator tick rate (ticks/s)
+host_mem_usage 230756 # Number of bytes of host memory used
+host_seconds 229.29 # Real time elapsed on the host
sim_insts 272739291 # Number of instructions simulated
sim_ops 348687131 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 437312 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
system.cpu.num_func_calls 12433363 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 18102313 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 18087061 # number of instructions that are conditional controls
system.cpu.num_int_insts 279584925 # number of integer instructions
system.cpu.num_fp_insts 114216705 # number of float instructions
system.cpu.num_int_register_reads 2212913209 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:22:39
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:18:43
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
2000: 760651391
1000: 4031656975
0: 2206428413
-Exiting @ tick 736384204000 because target called exit()
+Exiting @ tick 735495062500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.736384 # Number of seconds simulated
-sim_ticks 736384204000 # Number of ticks simulated
-final_tick 736384204000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.735495 # Number of seconds simulated
+sim_ticks 735495062500 # Number of ticks simulated
+final_tick 735495062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 107029 # Simulator instruction rate (inst/s)
-host_op_rate 145759 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 56931535 # Simulator tick rate (ticks/s)
-host_mem_usage 233236 # Number of bytes of host memory used
-host_seconds 12934.56 # Real time elapsed on the host
-sim_insts 1384379033 # Number of instructions simulated
-sim_ops 1885333786 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 94833536 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 209216 # Number of instructions bytes read from this memory
+host_inst_rate 126424 # Simulator instruction rate (inst/s)
+host_op_rate 172171 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 67166483 # Simulator tick rate (ticks/s)
+host_mem_usage 230552 # Number of bytes of host memory used
+host_seconds 10950.33 # Real time elapsed on the host
+sim_insts 1384379503 # Number of instructions simulated
+sim_ops 1885334256 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 94839680 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 213952 # Number of instructions bytes read from this memory
system.physmem.bytes_written 4230336 # Number of bytes written to this memory
-system.physmem.num_reads 1481774 # Number of read requests responded to by this memory
+system.physmem.num_reads 1481870 # Number of read requests responded to by this memory
system.physmem.num_writes 66099 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 128782686 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 284113 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 5744740 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 134527427 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 128946726 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 290895 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 5751685 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 134698411 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
-system.cpu.numCycles 1472768409 # number of cpu cycles simulated
+system.cpu.numCycles 1470990126 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 522739689 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 397666770 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 35592388 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 329507474 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 283194756 # Number of BTB hits
+system.cpu.BPredUnit.lookups 524657246 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 401089358 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 35661760 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 339540356 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 278948773 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 59112231 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 2837995 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 446610303 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2608281266 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 522739689 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 342306987 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 709905843 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 224599686 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 101691904 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2256 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 28872 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 415462379 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 10233497 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1441668699 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.553094 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.169508 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 59722038 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 2842670 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 444619593 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2613573524 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 524657246 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 338670811 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 712273911 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 223851331 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 98512911 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2271 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 29657 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 414743940 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 11577936 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1438039773 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.556437 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.167543 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 731812218 50.76% 50.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 54028478 3.75% 54.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 112774395 7.82% 62.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 69112712 4.79% 67.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 82239849 5.70% 72.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 54732676 3.80% 76.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 35582945 2.47% 79.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 33403067 2.32% 81.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 267982359 18.59% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 725823899 50.47% 50.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 56807029 3.95% 54.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 112550044 7.83% 62.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 69779758 4.85% 67.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 84813159 5.90% 73.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 53785792 3.74% 76.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 34099274 2.37% 79.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 30811930 2.14% 81.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 269568888 18.75% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1441668699 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.354937 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.771006 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 492629108 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 81861101 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 672684141 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 11080003 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 183414346 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 82040809 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 15532 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3552890515 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 32736 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 183414346 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 530589836 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 29829797 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 3588754 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 644081795 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 50164171 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 3435316942 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 112 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4205507 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 40993124 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 37 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 3332970891 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 16270156364 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 15618651087 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 651505277 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1993153599 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 1339817292 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 273156 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 268372 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 142469911 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 1057917040 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 579962844 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 32519670 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 39211966 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 3198933227 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 269334 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2725360235 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 26814777 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 1313459573 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3048227605 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 58004 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1441668699 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.890421 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.914096 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 1438039773 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.356669 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.776744 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 492128614 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 78582078 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 673411779 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 11338206 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 182579096 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 79653725 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 23825 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3539524175 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 54394 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 182579096 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 529782652 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 30198632 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 660985 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 645094382 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 49724026 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 3431194053 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 133 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 4188042 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 40587721 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 1707 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 3342681891 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 16249059655 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 15604311677 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 644747978 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1993154351 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 1349527540 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 64268 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 59597 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 138053548 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 1061160981 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 575711799 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 34121400 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 39206197 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 3192585936 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 69047 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2718019401 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 27726721 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 1306902480 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3048220381 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 45882 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1438039773 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.890086 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.916332 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 524357405 36.37% 36.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 197522511 13.70% 50.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 215009168 14.91% 64.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 179008270 12.42% 77.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 156604882 10.86% 88.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 103164450 7.16% 95.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 49203607 3.41% 98.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 11056090 0.77% 99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 5742316 0.40% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 521512118 36.27% 36.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 198246164 13.79% 50.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 216916723 15.08% 65.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 178677193 12.43% 77.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 155355732 10.80% 88.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 100852221 7.01% 95.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 48369591 3.36% 98.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 10873615 0.76% 99.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 7236416 0.50% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1441668699 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1438039773 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2118699 2.21% 2.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 23832 0.02% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 56614089 59.02% 61.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 37163288 38.74% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1743579 1.83% 1.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 23896 0.03% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 56969230 59.63% 61.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 36797024 38.52% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1266333715 46.46% 46.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 11230148 0.41% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 6876563 0.25% 47.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 5503497 0.20% 47.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 38 0.00% 47.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 23211520 0.85% 48.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 900219934 33.03% 81.26% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 510609530 18.74% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1258053988 46.29% 46.29% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 11231448 0.41% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 6876560 0.25% 47.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 5503486 0.20% 47.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 73 0.00% 47.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 23204970 0.85% 48.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 902246151 33.19% 81.25% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 509527435 18.75% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2725360235 # Type of FU issued
-system.cpu.iq.rate 1.850502 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 95919908 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.035195 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6880679936 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 4410033557 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2496172626 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 134443918 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 102684223 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 60255652 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2752299483 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 68980660 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 71230775 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2718019401 # Type of FU issued
+system.cpu.iq.rate 1.847748 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 95533729 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.035148 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6864166409 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 4398397135 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2490268759 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 133172616 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 101224152 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 59789124 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2745104459 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 68448671 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 72240187 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 426528171 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 281369 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 1323673 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 302965860 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 429772018 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 278201 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 1347099 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 298714721 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 92 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 183414346 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 16249953 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1608700 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 3199274316 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 7370103 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 1057917040 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 579962844 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 258370 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1607775 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 215 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 1323673 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 37204877 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 8928711 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 46133588 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2624820303 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 845791055 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 100539932 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 182579096 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 16373982 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1591067 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 3192732241 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 7809183 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 1061160981 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 575711799 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 58058 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1589162 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 317 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 1347099 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 36984086 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 8972300 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 45956386 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2617990910 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 846641153 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 100028491 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 71755 # number of nop insts executed
-system.cpu.iew.exec_refs 1327328363 # number of memory reference insts executed
-system.cpu.iew.exec_branches 362158100 # Number of branches executed
-system.cpu.iew.exec_stores 481537308 # Number of stores executed
-system.cpu.iew.exec_rate 1.782236 # Inst execution rate
-system.cpu.iew.wb_sent 2584846968 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2556428278 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1474733618 # num instructions producing a value
-system.cpu.iew.wb_consumers 2760579704 # num instructions consuming a value
+system.cpu.iew.exec_nop 77258 # number of nop insts executed
+system.cpu.iew.exec_refs 1326395495 # number of memory reference insts executed
+system.cpu.iew.exec_branches 359930496 # Number of branches executed
+system.cpu.iew.exec_stores 479754342 # Number of stores executed
+system.cpu.iew.exec_rate 1.779747 # Inst execution rate
+system.cpu.iew.wb_sent 2578580051 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2550057883 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1472840060 # num instructions producing a value
+system.cpu.iew.wb_consumers 2760220207 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.735798 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.534212 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.733566 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.533595 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 1384390049 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 1885344802 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 1313929852 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 211330 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 41115032 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1258254355 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.498381 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.211057 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 1384390519 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 1885345272 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 1307387427 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 23165 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 41179561 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1255460679 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.501716 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.213055 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 578553729 45.98% 45.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 316892144 25.19% 71.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 101707631 8.08% 79.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 79187361 6.29% 85.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 52970249 4.21% 89.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 24190672 1.92% 91.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 17058373 1.36% 93.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 9262849 0.74% 93.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 78431347 6.23% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 576199063 45.90% 45.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 316668907 25.22% 71.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 101245126 8.06% 79.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 79298067 6.32% 85.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 52885974 4.21% 89.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 24348674 1.94% 91.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 17176683 1.37% 93.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 9160932 0.73% 93.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 78477253 6.25% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1258254355 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 1384390049 # Number of instructions committed
-system.cpu.commit.committedOps 1885344802 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 1255460679 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 1384390519 # Number of instructions committed
+system.cpu.commit.committedOps 1885345272 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 908385853 # Number of memory references committed
-system.cpu.commit.loads 631388869 # Number of loads committed
+system.cpu.commit.refs 908386041 # Number of memory references committed
+system.cpu.commit.loads 631388963 # Number of loads committed
system.cpu.commit.membars 9986 # Number of memory barriers committed
-system.cpu.commit.branches 291350232 # Number of branches committed
+system.cpu.commit.branches 291350326 # Number of branches committed
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1653705623 # Number of committed integer instructions.
+system.cpu.commit.int_insts 1653705999 # Number of committed integer instructions.
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 78431347 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 78477253 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 4379079317 # The number of ROB reads
-system.cpu.rob.rob_writes 6581974646 # The number of ROB writes
-system.cpu.timesIdled 1328714 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 31099710 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1384379033 # Number of Instructions Simulated
-system.cpu.committedOps 1885333786 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 1384379033 # Number of Instructions Simulated
-system.cpu.cpi 1.063848 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.063848 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.939984 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.939984 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 12935043618 # number of integer regfile reads
-system.cpu.int_regfile_writes 2425775909 # number of integer regfile writes
-system.cpu.fp_regfile_reads 71439411 # number of floating regfile reads
-system.cpu.fp_regfile_writes 51051626 # number of floating regfile writes
-system.cpu.misc_regfile_reads 4084910091 # number of misc regfile reads
-system.cpu.misc_regfile_writes 13776276 # number of misc regfile writes
-system.cpu.icache.replacements 28501 # number of replacements
-system.cpu.icache.tagsinuse 1662.292931 # Cycle average of tags in use
-system.cpu.icache.total_refs 415426412 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 30198 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 13756.752500 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 4369697780 # The number of ROB reads
+system.cpu.rob.rob_writes 6568059146 # The number of ROB writes
+system.cpu.timesIdled 1341236 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 32950353 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 1384379503 # Number of Instructions Simulated
+system.cpu.committedOps 1885334256 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 1384379503 # Number of Instructions Simulated
+system.cpu.cpi 1.062563 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.062563 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.941121 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.941121 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 12914363689 # number of integer regfile reads
+system.cpu.int_regfile_writes 2421503464 # number of integer regfile writes
+system.cpu.fp_regfile_reads 71102089 # number of floating regfile reads
+system.cpu.fp_regfile_writes 50855882 # number of floating regfile writes
+system.cpu.misc_regfile_reads 4088825153 # number of misc regfile reads
+system.cpu.misc_regfile_writes 13776464 # number of misc regfile writes
+system.cpu.icache.replacements 29072 # number of replacements
+system.cpu.icache.tagsinuse 1666.420003 # Cycle average of tags in use
+system.cpu.icache.total_refs 414707358 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 30775 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 13475.462486 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1662.292931 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.811666 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.811666 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 415426419 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 415426419 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 415426419 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 415426419 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 415426419 # number of overall hits
-system.cpu.icache.overall_hits::total 415426419 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 35960 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 35960 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 35960 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 35960 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 35960 # number of overall misses
-system.cpu.icache.overall_misses::total 35960 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 314726500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 314726500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 314726500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 314726500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 314726500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 314726500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 415462379 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 415462379 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 415462379 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 415462379 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 415462379 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 415462379 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8752.127364 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 8752.127364 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 8752.127364 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1666.420003 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.813682 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.813682 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 414707364 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 414707364 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 414707364 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 414707364 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 414707364 # number of overall hits
+system.cpu.icache.overall_hits::total 414707364 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 36576 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 36576 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 36576 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 36576 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 36576 # number of overall misses
+system.cpu.icache.overall_misses::total 36576 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 322136500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 322136500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 322136500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 322136500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 322136500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 322136500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 414743940 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 414743940 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 414743940 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 414743940 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 414743940 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 414743940 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8807.319007 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 780 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 780 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 780 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 780 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 780 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 780 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 35180 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 35180 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 35180 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 35180 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 35180 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 35180 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 188682500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 188682500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 188682500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 188682500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 188682500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 188682500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5363.345651 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5363.345651 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5363.345651 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 853 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 853 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 853 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 853 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 853 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 853 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 35723 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 35723 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 35723 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 35723 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 35723 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 35723 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192601000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 192601000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192601000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 192601000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192601000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 192601000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5391.512471 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1532334 # number of replacements
-system.cpu.dcache.tagsinuse 4094.808393 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1033081236 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1536430 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 672.390695 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 312649000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4094.808393 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999709 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999709 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 756924525 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 756924525 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 276114347 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 276114347 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 12957 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 12957 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 11669 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 11669 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 1033038872 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1033038872 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1033038872 # number of overall hits
-system.cpu.dcache.overall_hits::total 1033038872 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2432909 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2432909 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 821331 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 821331 # number of WriteReq misses
+system.cpu.dcache.replacements 1532415 # number of replacements
+system.cpu.dcache.tagsinuse 4094.914319 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1032974400 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1536511 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 672.285717 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 290267000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4094.914319 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999735 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999735 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 756817928 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 756817928 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 276114576 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 276114576 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 13150 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 13150 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 11766 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 11766 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 1032932504 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1032932504 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1032932504 # number of overall hits
+system.cpu.dcache.overall_hits::total 1032932504 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2368566 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2368566 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 821102 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 821102 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 3254240 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3254240 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3254240 # number of overall misses
-system.cpu.dcache.overall_misses::total 3254240 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 81657017500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 81657017500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 28588903000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 28588903000 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 108000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 108000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 16500 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 16500 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 110245920500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 110245920500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 110245920500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 110245920500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 759357434 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 759357434 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 3189668 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3189668 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3189668 # number of overall misses
+system.cpu.dcache.overall_misses::total 3189668 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 80139479500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 80139479500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 28569168500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 28569168500 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 114500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 114500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 108708648000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 108708648000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 108708648000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 108708648000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 759186494 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 759186494 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12960 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 12960 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 11672 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 11672 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 1036293112 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 1036293112 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 1036293112 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 1036293112 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003204 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002966 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000231 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000257 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.003140 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.003140 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33563.531353 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34808.016500 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 36000 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 5500 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 33877.624422 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 33877.624422 # average overall miss latency
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13153 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 13153 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 11766 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 11766 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 1036122172 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 1036122172 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 1036122172 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 1036122172 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003120 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002965 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000228 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.003078 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.003078 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33834.598445 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34793.690065 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38166.666667 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 80000 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 81500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 20375 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 106562 # number of writebacks
-system.cpu.dcache.writebacks::total 106562 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 969189 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 969189 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743643 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 743643 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 106560 # number of writebacks
+system.cpu.dcache.writebacks::total 106560 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904767 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 904767 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743443 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 743443 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1712832 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1712832 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1712832 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1712832 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1463720 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1463720 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77688 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 77688 # number of WriteReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1541408 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1541408 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1541408 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1541408 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50029308500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 50029308500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2504136000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2504136000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 7500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 7500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52533444500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 52533444500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52533444500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 52533444500 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data 1648210 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1648210 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1648210 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1648210 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1463799 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1463799 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77659 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 77659 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1541458 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1541458 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1541458 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1541458 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50029877000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 50029877000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2502958500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2502958500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52532835500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 52532835500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52532835500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 52532835500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001928 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000281 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000257 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001487 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001487 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34179.562006 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32233.240655 # average WriteReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 2500 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34081.466101 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34081.466101 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34178.105737 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32230.114990 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 1480213 # number of replacements
-system.cpu.l2cache.tagsinuse 31972.758917 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 86473 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 1512931 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.057156 # Average number of references to valid blocks.
+system.cpu.l2cache.replacements 1480284 # number of replacements
+system.cpu.l2cache.tagsinuse 31973.508020 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 87070 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 1513005 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.057548 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 2964.503438 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 60.794216 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 28947.461262 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.090469 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.001855 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.883406 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.975731 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 26928 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 51269 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 78197 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 106562 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 106562 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 6630 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 6630 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 26928 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 57899 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 84827 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 26928 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 57899 # number of overall hits
-system.cpu.l2cache.overall_hits::total 84827 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3274 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 1412451 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 1415725 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 4973 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 4973 # number of UpgradeReq misses
+system.cpu.l2cache.occ_blocks::writebacks 2965.813236 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 61.172380 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 28946.522403 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.090509 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.001867 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.883378 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.975754 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 27428 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 51328 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 78756 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 106560 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 106560 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 6632 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 6632 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 27428 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 57960 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 85388 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 27428 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 57960 # number of overall hits
+system.cpu.l2cache.overall_hits::total 85388 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3348 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 1412471 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 1415819 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 4944 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 4944 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 66080 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 66080 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3274 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 1478531 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 1481805 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3274 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 1478531 # number of overall misses
-system.cpu.l2cache.overall_misses::total 1481805 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 112237000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48455418000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 48567655000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2252377500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 2252377500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 112237000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 50707795500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 50820032500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 112237000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 50707795500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 50820032500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 30202 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1463720 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1493922 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 106562 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 106562 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4978 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 4978 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 3 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 72710 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 72710 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 30202 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1536430 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1566632 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 30202 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1536430 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1566632 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.108403 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964973 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.998996 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908816 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.108403 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.962316 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.108403 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.962316 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34281.307269 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34305.910789 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34085.615920 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34281.307269 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.065148 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34281.307269 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.065148 # average overall miss latency
+system.cpu.l2cache.demand_misses::cpu.inst 3348 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 1478551 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 1481899 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3348 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 1478551 # number of overall misses
+system.cpu.l2cache.overall_misses::total 1481899 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 114766000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48456356500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 48571122500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2252292000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2252292000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 114766000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 50708648500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 50823414500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 114766000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 50708648500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 50823414500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 30776 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1463799 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1494575 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 106560 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 106560 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4947 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 4947 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 72712 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 72712 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 30776 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1536511 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1567287 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 30776 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1536511 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1567287 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.108786 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964935 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999394 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908791 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.108786 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.962278 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.108786 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.962278 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.972521 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34306.089470 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34084.322034 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks
system.cpu.l2cache.writebacks::total 66099 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 26 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 31 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3269 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1412425 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1415694 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4973 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 4973 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3343 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1412447 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1415790 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4944 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 4944 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66080 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66080 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3269 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 1478505 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 1481774 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3269 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1478505 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 1481774 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 101602500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43882479500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43984082000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 154163000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 154163000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048540000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048540000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 101602500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45931019500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 46032622000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101602500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45931019500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 46032622000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108238 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964956 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.998996 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908816 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108238 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962299 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108238 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962299 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31080.605690 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.891800 # average ReadReq mshr miss latency
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3343 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1478527 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 1481870 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3343 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1478527 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 1481870 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103877000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43883033500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43986910500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 153264000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 153264000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048525000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048525000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103877000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45931558500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 46035435500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103877000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45931558500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 46035435500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964919 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999394 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908791 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31072.988334 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.800104 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.907990 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31080.605690 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.853345 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31080.605690 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.853345 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.680993 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 16:09:56
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:20:21
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 945613131000 # Number of ticks simulated
final_tick 945613131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2461578 # Simulator instruction rate (inst/s)
-host_op_rate 3352328 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1681400523 # Simulator tick rate (ticks/s)
-host_mem_usage 221408 # Number of bytes of host memory used
-host_seconds 562.40 # Real time elapsed on the host
+host_inst_rate 2176707 # Simulator instruction rate (inst/s)
+host_op_rate 2964374 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1486817392 # Simulator tick rate (ticks/s)
+host_mem_usage 218836 # Number of bytes of host memory used
+host_seconds 636.00 # Real time elapsed on the host
sim_insts 1384381614 # Number of instructions simulated
sim_ops 1885336367 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 8025491315 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
system.cpu.num_func_calls 80344203 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 223764558 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 223735906 # number of instructions that are conditional controls
system.cpu.num_int_insts 1653698876 # number of integer instructions
system.cpu.num_fp_insts 52289415 # number of float instructions
system.cpu.num_int_register_reads 8601515950 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 16:19:22
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:31:08
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 2369901960000 # Number of ticks simulated
final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1323415 # Simulator instruction rate (inst/s)
-host_op_rate 1795307 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2270088736 # Simulator tick rate (ticks/s)
-host_mem_usage 230320 # Number of bytes of host memory used
-host_seconds 1043.97 # Real time elapsed on the host
+host_inst_rate 1363943 # Simulator instruction rate (inst/s)
+host_op_rate 1850286 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2339607262 # Simulator tick rate (ticks/s)
+host_mem_usage 227748 # Number of bytes of host memory used
+host_seconds 1012.95 # Real time elapsed on the host
sim_insts 1381604347 # Number of instructions simulated
sim_ops 1874244950 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 94696320 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
system.cpu.num_func_calls 80344203 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 223764558 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 223735906 # number of instructions that are conditional controls
system.cpu.num_int_insts 1653698876 # number of integer instructions
system.cpu.num_fp_insts 52289415 # number of float instructions
system.cpu.num_int_register_reads 10466679954 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:25:21
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:35:27
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 30755543500 because target called exit()
+Exiting @ tick 24560764000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.030756 # Number of seconds simulated
-sim_ticks 30755543500 # Number of ticks simulated
-final_tick 30755543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.024561 # Number of seconds simulated
+sim_ticks 24560764000 # Number of ticks simulated
+final_tick 24560764000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 147147 # Simulator instruction rate (inst/s)
-host_op_rate 208812 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 63815156 # Simulator tick rate (ticks/s)
-host_mem_usage 235936 # Number of bytes of host memory used
-host_seconds 481.95 # Real time elapsed on the host
-sim_insts 70917252 # Number of instructions simulated
-sim_ops 100636500 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 8681216 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 364288 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 5661440 # Number of bytes written to this memory
-system.physmem.num_reads 135644 # Number of read requests responded to by this memory
-system.physmem.num_writes 88460 # Number of write requests responded to by this memory
+host_inst_rate 175313 # Simulator instruction rate (inst/s)
+host_op_rate 248779 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 60713797 # Simulator tick rate (ticks/s)
+host_mem_usage 233096 # Number of bytes of host memory used
+host_seconds 404.53 # Real time elapsed on the host
+sim_insts 70920072 # Number of instructions simulated
+sim_ops 100639320 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 8687232 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 367552 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 5661632 # Number of bytes written to this memory
+system.physmem.num_reads 135738 # Number of read requests responded to by this memory
+system.physmem.num_writes 88463 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 282265082 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 11844629 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 184078685 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 466343767 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 353703655 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 14965007 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 230515305 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 584218960 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 61511088 # number of cpu cycles simulated
+system.cpu.numCycles 49121529 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 17165899 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 13150342 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 741670 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 12130394 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 8128680 # Number of BTB hits
+system.cpu.BPredUnit.lookups 17484643 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 13346532 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 763895 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 12042742 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 8272877 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1854457 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 183977 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 13000354 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 87655737 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 17165899 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9983137 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21873848 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2772277 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 23278441 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 2074 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 12226708 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 230090 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 60107424 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.046912 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.144766 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1873235 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 186435 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 13233353 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 89314081 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 17484643 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 10146112 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 22235900 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 3054378 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 9993886 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 494 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 12432222 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 242141 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 47666513 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.625620 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.342151 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 38251797 63.64% 63.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2252747 3.75% 67.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1977441 3.29% 70.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2053713 3.42% 74.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1587290 2.64% 76.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1440263 2.40% 79.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 985496 1.64% 80.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1267048 2.11% 82.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 10291629 17.12% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 25452916 53.40% 53.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2276272 4.78% 58.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2010669 4.22% 62.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2082167 4.37% 66.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1606372 3.37% 70.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1473384 3.09% 73.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1003270 2.10% 75.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1293693 2.71% 78.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 10467770 21.96% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 60107424 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.279070 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.425040 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 14856562 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 22001240 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 20371729 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1031804 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1846089 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3466450 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 109251 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 119897530 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 366577 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1846089 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 16668221 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1965297 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 15638738 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 19567499 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4421580 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 116607925 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4528 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 3022237 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 40 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 116831766 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 536941360 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 536932869 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 8491 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 99148069 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 17683697 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 794887 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 794929 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12663863 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29905745 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 22497839 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2550433 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 3605599 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 111646205 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 783462 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 107783359 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 315194 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 11596172 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 28526322 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 79963 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 60107424 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.793179 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.923398 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 47666513 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.355947 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.818227 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 15402794 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 8395926 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 20419082 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1357324 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2091387 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3552582 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 114889 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 122010152 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 381349 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2091387 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 17235553 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2381046 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 774700 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 19895179 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5288648 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 118965286 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 65 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 10051 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4471697 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 173 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 119289544 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 547314245 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 547305502 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 8743 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 99152581 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 20136963 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 50089 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 50062 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12897670 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 30342934 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 22764283 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 3373932 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 4070444 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 114201865 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 59946 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 108885427 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 355885 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 13447173 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 32642565 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 23673 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 47666513 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.284317 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.003120 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 21602316 35.94% 35.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 11403464 18.97% 54.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8200759 13.64% 68.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7319332 12.18% 80.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4922118 8.19% 88.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3558954 5.92% 94.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1700735 2.83% 97.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 865239 1.44% 99.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 534507 0.89% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 11902735 24.97% 24.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 8314690 17.44% 42.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7496951 15.73% 58.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7072171 14.84% 72.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 5553695 11.65% 84.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3902484 8.19% 92.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1926147 4.04% 96.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 904880 1.90% 98.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 592760 1.24% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 60107424 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 47666513 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 107169 4.01% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1504678 56.36% 60.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 1057992 39.63% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 112261 4.35% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1423319 55.12% 59.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 1046695 40.53% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 56937666 52.83% 52.83% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 88934 0.08% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 306 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.91% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 29100662 27.00% 79.91% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 21655782 20.09% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 57627292 52.92% 52.92% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 88925 0.08% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 277 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.01% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 29380371 26.98% 79.99% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 21788555 20.01% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 107783359 # Type of FU issued
-system.cpu.iq.rate 1.752259 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2669841 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.024770 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 278658374 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 124040880 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 105647232 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 803 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1299 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 239 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 110452800 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 400 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1897681 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 108885427 # Type of FU issued
+system.cpu.iq.rate 2.216654 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2582277 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.023716 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 268374678 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 127734912 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 106613834 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 851 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1416 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 211 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 111467277 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 427 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 2219770 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2596713 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 5092 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 17660 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1940178 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3033338 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 8348 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 28761 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2206058 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 48 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 61 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 47 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 51 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1846089 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 949061 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 28680 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 112509386 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 471926 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29905745 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 22497839 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 767420 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1122 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1174 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 17660 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 518600 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 257124 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 775724 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 106553535 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 28745908 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1229824 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 2091387 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 991755 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 31052 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 114342127 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 442332 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 30342934 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 22764283 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 43712 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1891 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 1967 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 28761 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 532244 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 266639 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 798883 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 107583415 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 28980389 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1302012 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 79719 # number of nop insts executed
-system.cpu.iew.exec_refs 50100729 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14610772 # Number of branches executed
-system.cpu.iew.exec_stores 21354821 # Number of stores executed
-system.cpu.iew.exec_rate 1.732265 # Inst execution rate
-system.cpu.iew.wb_sent 105985847 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 105647471 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 52628676 # num instructions producing a value
-system.cpu.iew.wb_consumers 101773898 # num instructions consuming a value
+system.cpu.iew.exec_nop 80316 # number of nop insts executed
+system.cpu.iew.exec_refs 50461236 # number of memory reference insts executed
+system.cpu.iew.exec_branches 14752818 # Number of branches executed
+system.cpu.iew.exec_stores 21480847 # Number of stores executed
+system.cpu.iew.exec_rate 2.190148 # Inst execution rate
+system.cpu.iew.wb_sent 106971474 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 106614045 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 53628736 # num instructions producing a value
+system.cpu.iew.wb_consumers 104822222 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.717535 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.517114 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.170414 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.511616 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 70922804 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 100642052 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 11867683 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 703499 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 697454 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 58261336 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.727424 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.444675 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 70925624 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 100644872 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 13697900 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 36273 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 715054 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 45575127 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.208329 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.734720 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 25494739 43.76% 43.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 14514509 24.91% 68.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4165612 7.15% 75.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3613399 6.20% 82.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2299623 3.95% 85.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1924742 3.30% 89.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 677832 1.16% 90.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 500112 0.86% 91.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5070768 8.70% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 16228357 35.61% 35.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11797211 25.89% 61.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3508330 7.70% 69.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2972714 6.52% 75.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1972056 4.33% 80.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1932722 4.24% 84.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 698627 1.53% 85.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 551617 1.21% 87.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5913493 12.98% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 58261336 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 70922804 # Number of instructions committed
-system.cpu.commit.committedOps 100642052 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 45575127 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 70925624 # Number of instructions committed
+system.cpu.commit.committedOps 100644872 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 47866693 # Number of memory references committed
-system.cpu.commit.loads 27309032 # Number of loads committed
+system.cpu.commit.refs 47867821 # Number of memory references committed
+system.cpu.commit.loads 27309596 # Number of loads committed
system.cpu.commit.membars 15920 # Number of memory barriers committed
-system.cpu.commit.branches 13670551 # Number of branches committed
+system.cpu.commit.branches 13671115 # Number of branches committed
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 91480479 # Number of committed integer instructions.
+system.cpu.commit.int_insts 91482735 # Number of committed integer instructions.
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5070768 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5913493 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 165675004 # The number of ROB reads
-system.cpu.rob.rob_writes 226873042 # The number of ROB writes
-system.cpu.timesIdled 61564 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 1403664 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 70917252 # Number of Instructions Simulated
-system.cpu.committedOps 100636500 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 70917252 # Number of Instructions Simulated
-system.cpu.cpi 0.867364 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.867364 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.152918 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.152918 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 512909735 # number of integer regfile reads
-system.cpu.int_regfile_writes 103521788 # number of integer regfile writes
-system.cpu.fp_regfile_reads 1198 # number of floating regfile reads
-system.cpu.fp_regfile_writes 998 # number of floating regfile writes
-system.cpu.misc_regfile_reads 145684870 # number of misc regfile reads
-system.cpu.misc_regfile_writes 35686 # number of misc regfile writes
-system.cpu.icache.replacements 28916 # number of replacements
-system.cpu.icache.tagsinuse 1823.894979 # Cycle average of tags in use
-system.cpu.icache.total_refs 12194402 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 30952 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 393.977837 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 153979107 # The number of ROB reads
+system.cpu.rob.rob_writes 230788170 # The number of ROB writes
+system.cpu.timesIdled 64143 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 1455016 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 70920072 # Number of Instructions Simulated
+system.cpu.committedOps 100639320 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 70920072 # Number of Instructions Simulated
+system.cpu.cpi 0.692632 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.692632 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.443768 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.443768 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 517371049 # number of integer regfile reads
+system.cpu.int_regfile_writes 104514948 # number of integer regfile writes
+system.cpu.fp_regfile_reads 1051 # number of floating regfile reads
+system.cpu.fp_regfile_writes 886 # number of floating regfile writes
+system.cpu.misc_regfile_reads 147913903 # number of misc regfile reads
+system.cpu.misc_regfile_writes 36814 # number of misc regfile writes
+system.cpu.icache.replacements 31518 # number of replacements
+system.cpu.icache.tagsinuse 1822.469235 # Cycle average of tags in use
+system.cpu.icache.total_refs 12397113 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 33561 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 369.390453 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1823.894979 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.890574 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.890574 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 12194406 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 12194406 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 12194406 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 12194406 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 12194406 # number of overall hits
-system.cpu.icache.overall_hits::total 12194406 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 32302 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 32302 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 32302 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 32302 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 32302 # number of overall misses
-system.cpu.icache.overall_misses::total 32302 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 385546000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 385546000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 385546000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 385546000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 385546000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 385546000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 12226708 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 12226708 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 12226708 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 12226708 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 12226708 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 12226708 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002642 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.002642 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.002642 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11935.669618 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 11935.669618 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 11935.669618 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1822.469235 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.889878 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.889878 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 12397114 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 12397114 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 12397114 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 12397114 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 12397114 # number of overall hits
+system.cpu.icache.overall_hits::total 12397114 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 35108 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 35108 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 35108 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 35108 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 35108 # number of overall misses
+system.cpu.icache.overall_misses::total 35108 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 406151000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 406151000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 406151000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 406151000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 406151000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 406151000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 12432222 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 12432222 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 12432222 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 12432222 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 12432222 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 12432222 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002824 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.002824 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.002824 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11568.616839 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1300 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 1300 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 1300 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 1300 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 1300 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 1300 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31002 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 31002 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 31002 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 31002 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 31002 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 31002 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 260426000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 260426000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 260426000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 260426000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 260426000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 260426000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002536 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002536 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002536 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8400.296755 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8400.296755 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8400.296755 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1474 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 1474 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 1474 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 1474 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 1474 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 1474 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33634 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 33634 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 33634 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 33634 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 33634 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 33634 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268782500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 268782500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268782500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 268782500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268782500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 268782500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7991.392638 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 158739 # number of replacements
-system.cpu.dcache.tagsinuse 4072.206882 # Cycle average of tags in use
-system.cpu.dcache.total_refs 44824724 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 162835 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 275.276961 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 306509000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4072.206882 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.994191 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.994191 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 26477714 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 26477714 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18310173 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18310173 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 18862 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 18862 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 17842 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 17842 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 44787887 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 44787887 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 44787887 # number of overall hits
-system.cpu.dcache.overall_hits::total 44787887 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 109145 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 109145 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1539728 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1539728 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 32 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 32 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 1648873 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1648873 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1648873 # number of overall misses
-system.cpu.dcache.overall_misses::total 1648873 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 2419748500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 2419748500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 52564184000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 52564184000 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 414000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 414000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 54983932500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 54983932500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 54983932500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 54983932500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 26586859 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 26586859 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements 158907 # number of replacements
+system.cpu.dcache.tagsinuse 4070.754102 # Cycle average of tags in use
+system.cpu.dcache.total_refs 44741379 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 163003 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 274.481936 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 274553000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4070.754102 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.993836 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.993836 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 26393302 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 26393302 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 18309799 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 18309799 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 19644 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 19644 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 18406 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 18406 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 44703101 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 44703101 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 44703101 # number of overall hits
+system.cpu.dcache.overall_hits::total 44703101 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 110193 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 110193 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1540102 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1540102 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 35 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 35 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 1650295 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1650295 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1650295 # number of overall misses
+system.cpu.dcache.overall_misses::total 1650295 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 2434975500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 2434975500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 52525381000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 52525381000 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 425000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 425000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 54960356500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 54960356500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 54960356500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 54960356500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 26503495 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 26503495 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 18894 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 18894 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 17842 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 17842 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 46436760 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 46436760 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 46436760 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 46436760 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004105 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077569 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001694 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.035508 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.035508 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22170.035274 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34138.616691 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12937.500000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 33346.372037 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 33346.372037 # average overall miss latency
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 19679 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 19679 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 18406 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 18406 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 46353396 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 46353396 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 46353396 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 46353396 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004158 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077587 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001779 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.035602 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.035602 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22097.370069 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34105.131348 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12142.857143 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 199000 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 203500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 19900 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 123771 # number of writebacks
-system.cpu.dcache.writebacks::total 123771 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53183 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 53183 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1432805 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1432805 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 32 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 32 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1485988 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1485988 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1485988 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1485988 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55962 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 55962 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106923 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 106923 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 162885 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 162885 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 162885 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 162885 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1045315000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 1045315000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3667070000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3667070000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4712385000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 4712385000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4712385000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 4712385000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005387 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003508 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003508 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18679.014331 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34296.362803 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28930.748688 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28930.748688 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 123795 # number of writebacks
+system.cpu.dcache.writebacks::total 123795 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54073 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 54073 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1433145 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1433145 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 35 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 35 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1487218 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1487218 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1487218 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1487218 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56120 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 56120 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106957 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 106957 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 163077 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 163077 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 163077 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 163077 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1049489500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 1049489500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3666942000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3666942000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4716431500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 4716431500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4716431500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 4716431500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005388 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18700.810763 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34284.263770 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 115379 # number of replacements
-system.cpu.l2cache.tagsinuse 18377.888131 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 75936 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 134247 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.565644 # Average number of references to valid blocks.
+system.cpu.l2cache.replacements 115487 # number of replacements
+system.cpu.l2cache.tagsinuse 18346.494934 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 78611 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 134352 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.585112 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 15924.740551 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 876.929097 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 1576.218483 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.485985 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.026762 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.048102 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.560849 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 25235 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 28501 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 53736 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 123771 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 123771 # number of Writeback hits
+system.cpu.l2cache.occ_blocks::writebacks 15851.533035 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 880.199051 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1614.762848 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.483750 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.026862 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.049279 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.559891 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 27786 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 28611 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 56397 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 123795 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 123795 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 11 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 11 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 4314 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 4314 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 25235 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 32815 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 58050 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 25235 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 32815 # number of overall hits
-system.cpu.l2cache.overall_hits::total 58050 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 5715 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 27425 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 33140 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 39 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 39 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 102595 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 102595 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 5715 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 130020 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 135735 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 5715 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 130020 # number of overall misses
-system.cpu.l2cache.overall_misses::total 135735 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 195685000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 938760000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 1134445000 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 34000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 34000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3518172500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 3518172500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 195685000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 4456932500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 4652617500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 195685000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 4456932500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 4652617500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 30950 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 55926 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 86876 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 123771 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 123771 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 50 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 50 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 106909 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 106909 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 30950 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 162835 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 193785 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 30950 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 162835 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 193785 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.184653 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.490380 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780000 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959648 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.184653 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.798477 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.184653 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.798477 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34240.594926 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34230.082042 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 871.794872 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34291.851455 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34240.594926 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34278.822489 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34240.594926 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34278.822489 # average overall miss latency
+system.cpu.l2cache.ReadExReq_hits::cpu.data 4332 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 4332 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 27786 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 32943 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 60729 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 27786 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 32943 # number of overall hits
+system.cpu.l2cache.overall_hits::total 60729 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 5769 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 27473 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 33242 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 63 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 63 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 102587 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 102587 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 5769 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 130060 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 135829 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 5769 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 130060 # number of overall misses
+system.cpu.l2cache.overall_misses::total 135829 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 197487500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 940646500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1138134000 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 34500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 34500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3520234000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 3520234000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 197487500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 4460880500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 4658368000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 197487500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 4460880500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 4658368000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 33555 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 56084 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 89639 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 123795 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 123795 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 74 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 106919 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 106919 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 33555 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 163003 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 196558 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 33555 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 163003 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 196558 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171927 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.489855 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.851351 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959483 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.171927 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.797899 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.171927 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.797899 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34232.535968 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34238.943690 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 547.619048 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34314.620761 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34232.535968 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34298.635245 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34232.535968 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34298.635245 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 88460 # number of writebacks
-system.cpu.l2cache.writebacks::total 88460 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 23 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 67 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 67 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 90 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5692 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27358 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 33050 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 39 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 39 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102595 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 102595 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 5692 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 129953 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 135645 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 5692 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 129953 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 135645 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176784500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 850283000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1027067500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1211000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1211000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3193896000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3193896000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176784500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4044179000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 4220963500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176784500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4044179000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 4220963500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.183910 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.489182 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.780000 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959648 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.183910 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.798066 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.183910 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.798066 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31058.415320 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31079.866949 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31051.282051 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31131.107754 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31058.415320 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31120.320424 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31058.415320 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31120.320424 # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks 88463 # number of writebacks
+system.cpu.l2cache.writebacks::total 88463 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 26 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 26 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 91 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5743 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27408 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 33151 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 63 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 63 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102587 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 102587 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 5743 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 129995 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 135738 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 5743 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 129995 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 135738 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 178439000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 852007500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1030446500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1955000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1955000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3195019500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3195019500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178439000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4047027000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 4225466000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178439000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4047027000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 4225466000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.488696 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.851351 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959483 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31070.694759 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31086.088004 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.746032 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31144.487118 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 16:26:23
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:42:22
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 53932162000 # Number of ticks simulated
final_tick 53932162000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2398112 # Simulator instruction rate (inst/s)
-host_op_rate 3403143 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1823852749 # Simulator tick rate (ticks/s)
-host_mem_usage 223920 # Number of bytes of host memory used
-host_seconds 29.57 # Real time elapsed on the host
+host_inst_rate 2274185 # Simulator instruction rate (inst/s)
+host_op_rate 3227279 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1729602132 # Simulator tick rate (ticks/s)
+host_mem_usage 221076 # Number of bytes of host memory used
+host_seconds 31.18 # Real time elapsed on the host
sim_insts 70913189 # Number of instructions simulated
sim_ops 100632437 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 419153654 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
system.cpu.num_func_calls 3287514 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 10735849 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 10711743 # number of instructions that are conditional controls
system.cpu.num_int_insts 91472788 # number of integer instructions
system.cpu.num_fp_insts 56 # number of float instructions
system.cpu.num_int_register_reads 452177233 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 16:27:02
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:43:04
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 133117442000 # Number of ticks simulated
final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1310173 # Simulator instruction rate (inst/s)
-host_op_rate 1857860 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2478297620 # Simulator tick rate (ticks/s)
-host_mem_usage 232836 # Number of bytes of host memory used
-host_seconds 53.71 # Real time elapsed on the host
+host_inst_rate 1304890 # Simulator instruction rate (inst/s)
+host_op_rate 1850368 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2468304183 # Simulator tick rate (ticks/s)
+host_mem_usage 230248 # Number of bytes of host memory used
+host_seconds 53.93 # Real time elapsed on the host
sim_insts 70373636 # Number of instructions simulated
sim_ops 99791663 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 8570688 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
system.cpu.num_func_calls 3287514 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 10735849 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 10711743 # number of instructions that are conditional controls
system.cpu.num_int_insts 91472788 # number of integer instructions
system.cpu.num_fp_insts 56 # number of float instructions
system.cpu.num_int_register_reads 533542913 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:27:07
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:44:10
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 464094642500 because target called exit()
+Exiting @ tick 463993693500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.464095 # Number of seconds simulated
-sim_ticks 464094642500 # Number of ticks simulated
-final_tick 464094642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.463994 # Number of seconds simulated
+sim_ticks 463993693500 # Number of ticks simulated
+final_tick 463993693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 178110 # Simulator instruction rate (inst/s)
-host_op_rate 198694 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 53516537 # Simulator tick rate (ticks/s)
-host_mem_usage 227392 # Number of bytes of host memory used
-host_seconds 8671.99 # Real time elapsed on the host
-sim_insts 1544563041 # Number of instructions simulated
-sim_ops 1723073854 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 189817088 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 48640 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 78237376 # Number of bytes written to this memory
-system.physmem.num_reads 2965892 # Number of read requests responded to by this memory
-system.physmem.num_writes 1222459 # Number of write requests responded to by this memory
+host_inst_rate 212934 # Simulator instruction rate (inst/s)
+host_op_rate 237543 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 63966219 # Simulator tick rate (ticks/s)
+host_mem_usage 224764 # Number of bytes of host memory used
+host_seconds 7253.73 # Real time elapsed on the host
+sim_insts 1544563066 # Number of instructions simulated
+sim_ops 1723073879 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 189795648 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 49344 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 78222144 # Number of bytes written to this memory
+system.physmem.num_reads 2965557 # Number of read requests responded to by this memory
+system.physmem.num_writes 1222221 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 409005127 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 104806 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 168580649 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 577585776 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 409047904 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 106346 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 168584498 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 577632403 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 928189286 # number of cpu cycles simulated
+system.cpu.numCycles 927987388 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 300558884 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 246363041 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 16110008 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 171748174 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 156362542 # Number of BTB hits
+system.cpu.BPredUnit.lookups 300553850 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 246366147 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 16098585 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 170916236 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 156311774 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 18325675 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 390 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 292832773 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2158671516 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 300558884 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 174688217 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 429285540 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 83802150 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 129138530 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 283809493 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 5370008 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 918527985 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.613925 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.238783 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 18335288 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 425 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 292740519 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2158326699 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 300553850 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 174647062 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 429206926 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 83759589 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 129259054 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 200 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 283730265 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 5372560 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 918446800 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.613763 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.238744 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 489242491 53.26% 53.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 23031671 2.51% 55.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 38788083 4.22% 59.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 47826065 5.21% 65.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 40763412 4.44% 69.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 46954546 5.11% 74.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 39099426 4.26% 79.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 18124481 1.97% 80.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 174697810 19.02% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 489239924 53.27% 53.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 23020148 2.51% 55.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 38764254 4.22% 60.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 47809734 5.21% 65.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 40766066 4.44% 69.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 46976906 5.11% 74.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 39072572 4.25% 79.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 18137057 1.97% 80.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 174660139 19.02% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 918527985 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.323812 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.325680 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 322137890 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 109173401 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 403303983 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 16642613 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 67270098 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 46182318 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 747 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 2347171741 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2550 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 67270098 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 343773810 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 50758192 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 21988 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 397138305 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 59565592 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2290275122 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 23158 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4666704 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 46265569 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 2 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2264842596 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 10571584644 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 10571581459 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 3185 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1706319959 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 558522637 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 5679 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 5674 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 136915079 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 624891325 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 218844969 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 86018221 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 66187056 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2190772661 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1712 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2016120341 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 4885308 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 463006686 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1075673735 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1208 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 918527985 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.194947 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.923224 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 918446800 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.323877 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.325815 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 322039794 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 109288431 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 403236235 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 16643003 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 67239337 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 46165390 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 810 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 2346870217 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2646 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 67239337 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 343676895 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 50827249 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 9551 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 397069716 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 59624052 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2289998307 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 23088 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 4666333 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 46320806 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2264655243 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 10570139009 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 10570134861 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 4148 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1706319999 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 558335244 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 4462 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 4454 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 136929133 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 624839821 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 218742392 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 85961960 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 66558298 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2190567677 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 692 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2016055896 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 4892741 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 462785080 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1074735939 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 515 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 918446800 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.195071 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.923309 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 251260735 27.35% 27.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 138867546 15.12% 42.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 158222967 17.23% 59.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 116427032 12.68% 72.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 125736326 13.69% 86.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 75508875 8.22% 94.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 39162431 4.26% 98.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 10675084 1.16% 99.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2666989 0.29% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 251194344 27.35% 27.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 138877340 15.12% 42.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 158309179 17.24% 59.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 116273452 12.66% 72.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 125754756 13.69% 86.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 75525220 8.22% 94.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 39163504 4.26% 98.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 10678346 1.16% 99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2670659 0.29% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 918527985 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 918446800 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 822239 3.28% 3.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 4824 0.02% 3.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 824240 3.28% 3.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4827 0.02% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 19001190 75.81% 79.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 5234373 20.89% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 19025079 75.82% 79.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 5238831 20.88% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1234297815 61.22% 61.22% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 931066 0.05% 61.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1234276939 61.22% 61.22% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 932607 0.05% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 50 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 9 0.00% 61.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 61.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 29 0.00% 61.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 587044073 29.12% 90.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 193847304 9.61% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 587048024 29.12% 90.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 193798201 9.61% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2016120341 # Type of FU issued
-system.cpu.iq.rate 2.172100 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 25062626 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.012431 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4980716257 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2653967070 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1958162011 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 344 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 554 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2041182792 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 175 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 63608263 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2016055896 # Type of FU issued
+system.cpu.iq.rate 2.172504 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 25092977 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.012447 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4980543862 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2653539100 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1958126109 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 448 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 790 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2041148646 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 227 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 63700277 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 138964553 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 284704 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 189296 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 43997922 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 138913044 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 284373 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 189336 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 43895340 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 451252 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 451092 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 67270098 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 23165985 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1316827 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2190782552 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 5581738 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 624891325 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 218844969 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1648 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 207697 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 50017 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 189296 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 8647984 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 10198062 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 18846046 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1986617242 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 572452659 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 29503099 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 67239337 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 23164250 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1316440 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2190576494 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 5585867 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 624839821 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 218742392 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 626 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 207277 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 49894 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 189336 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 8626288 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 10208500 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 18834788 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1986583692 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 572477440 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 29472204 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 8179 # number of nop insts executed
-system.cpu.iew.exec_refs 763318356 # number of memory reference insts executed
-system.cpu.iew.exec_branches 238198091 # Number of branches executed
-system.cpu.iew.exec_stores 190865697 # Number of stores executed
-system.cpu.iew.exec_rate 2.140315 # Inst execution rate
-system.cpu.iew.wb_sent 1967150761 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1958162143 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1296167059 # num instructions producing a value
-system.cpu.iew.wb_consumers 2068734310 # num instructions consuming a value
+system.cpu.iew.exec_nop 8125 # number of nop insts executed
+system.cpu.iew.exec_refs 763312359 # number of memory reference insts executed
+system.cpu.iew.exec_branches 238194699 # Number of branches executed
+system.cpu.iew.exec_stores 190834919 # Number of stores executed
+system.cpu.iew.exec_rate 2.140744 # Inst execution rate
+system.cpu.iew.wb_sent 1967109112 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1958126281 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1296093484 # num instructions producing a value
+system.cpu.iew.wb_consumers 2068479796 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.109658 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.626551 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.110079 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.626592 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 1544563059 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 1723073872 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 467775476 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 504 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 16109498 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 851257888 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.024150 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.756084 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 1544563084 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 1723073897 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 467569115 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 177 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 16098007 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 851207464 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.024270 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.756192 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 363004636 42.64% 42.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 192697561 22.64% 65.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 73553862 8.64% 73.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 35091204 4.12% 78.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 18733793 2.20% 80.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 30684966 3.60% 83.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 19668934 2.31% 86.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10962087 1.29% 87.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106860845 12.55% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 362905349 42.63% 42.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 192760849 22.65% 65.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 73571189 8.64% 73.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 35131293 4.13% 78.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 18689200 2.20% 80.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 30622248 3.60% 83.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 19666355 2.31% 86.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 10977227 1.29% 87.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 106883754 12.56% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 851257888 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 1544563059 # Number of instructions committed
-system.cpu.commit.committedOps 1723073872 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 851207464 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 1544563084 # Number of instructions committed
+system.cpu.commit.committedOps 1723073897 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 660773819 # Number of memory references committed
-system.cpu.commit.loads 485926772 # Number of loads committed
+system.cpu.commit.refs 660773829 # Number of memory references committed
+system.cpu.commit.loads 485926777 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
-system.cpu.commit.branches 213462366 # Number of branches committed
+system.cpu.commit.branches 213462371 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions.
+system.cpu.commit.int_insts 1536941877 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 106860845 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 106883754 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2935245792 # The number of ROB reads
-system.cpu.rob.rob_writes 4449143808 # The number of ROB writes
-system.cpu.timesIdled 899784 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 9661301 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1544563041 # Number of Instructions Simulated
-system.cpu.committedOps 1723073854 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 1544563041 # Number of Instructions Simulated
-system.cpu.cpi 0.600940 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.600940 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.664060 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.664060 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 9952061686 # number of integer regfile reads
-system.cpu.int_regfile_writes 1938314522 # number of integer regfile writes
-system.cpu.fp_regfile_reads 132 # number of floating regfile reads
-system.cpu.fp_regfile_writes 135 # number of floating regfile writes
-system.cpu.misc_regfile_reads 2898335768 # number of misc regfile reads
-system.cpu.misc_regfile_writes 128 # number of misc regfile writes
-system.cpu.icache.replacements 24 # number of replacements
-system.cpu.icache.tagsinuse 636.409684 # Cycle average of tags in use
-system.cpu.icache.total_refs 283808312 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 793 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 357891.944515 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 2934966123 # The number of ROB reads
+system.cpu.rob.rob_writes 4448699546 # The number of ROB writes
+system.cpu.timesIdled 899596 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 9540588 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 1544563066 # Number of Instructions Simulated
+system.cpu.committedOps 1723073879 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 1544563066 # Number of Instructions Simulated
+system.cpu.cpi 0.600809 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.600809 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.664422 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.664422 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 9951953141 # number of integer regfile reads
+system.cpu.int_regfile_writes 1938266429 # number of integer regfile writes
+system.cpu.fp_regfile_reads 186 # number of floating regfile reads
+system.cpu.fp_regfile_writes 205 # number of floating regfile writes
+system.cpu.misc_regfile_reads 2897977277 # number of misc regfile reads
+system.cpu.misc_regfile_writes 138 # number of misc regfile writes
+system.cpu.icache.replacements 28 # number of replacements
+system.cpu.icache.tagsinuse 641.389873 # Cycle average of tags in use
+system.cpu.icache.total_refs 283729068 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 801 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 354218.561798 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 636.409684 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.310747 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.310747 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 283808312 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 283808312 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 283808312 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 283808312 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 283808312 # number of overall hits
-system.cpu.icache.overall_hits::total 283808312 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1181 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1181 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1181 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1181 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1181 # number of overall misses
-system.cpu.icache.overall_misses::total 1181 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 39284000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 39284000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 39284000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 39284000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 39284000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 39284000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 283809493 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 283809493 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 283809493 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 283809493 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 283809493 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 283809493 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 641.389873 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.313179 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.313179 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 283729068 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 283729068 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 283729068 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 283729068 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 283729068 # number of overall hits
+system.cpu.icache.overall_hits::total 283729068 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1197 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1197 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1197 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1197 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1197 # number of overall misses
+system.cpu.icache.overall_misses::total 1197 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 39840000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 39840000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 39840000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 39840000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 39840000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 39840000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 283730265 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 283730265 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 283730265 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 283730265 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 283730265 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 283730265 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33263.336156 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 33263.336156 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 33263.336156 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33283.208020 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 388 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 388 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 388 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 388 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 388 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 388 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 793 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 793 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 793 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 793 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 793 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27229500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 27229500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27229500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 27229500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27229500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 27229500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 396 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 396 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 396 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 396 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 396 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 396 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27579500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 27579500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27579500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 27579500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27579500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 27579500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34337.326608 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34337.326608 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34337.326608 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34431.335830 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 9619385 # number of replacements
-system.cpu.dcache.tagsinuse 4087.714803 # Cycle average of tags in use
-system.cpu.dcache.total_refs 660788859 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 9623481 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 68.664224 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 3348066000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4087.714803 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.997977 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.997977 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 493410063 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 493410063 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 167378645 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 167378645 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 88 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 88 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 63 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 63 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 660788708 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 660788708 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 660788708 # number of overall hits
-system.cpu.dcache.overall_hits::total 660788708 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 10697227 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 10697227 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 5207402 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 5207402 # number of WriteReq misses
+system.cpu.dcache.replacements 9619302 # number of replacements
+system.cpu.dcache.tagsinuse 4087.756066 # Cycle average of tags in use
+system.cpu.dcache.total_refs 660726669 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9623398 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 68.658354 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 3346373000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4087.756066 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.997987 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.997987 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 493348220 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 493348220 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 167378287 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 167378287 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 94 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 94 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 68 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 68 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 660726507 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 660726507 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 660726507 # number of overall hits
+system.cpu.dcache.overall_hits::total 660726507 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 10693817 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 10693817 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 5207760 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 5207760 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 15904629 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 15904629 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 15904629 # number of overall misses
-system.cpu.dcache.overall_misses::total 15904629 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 189148262000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 189148262000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 129349741794 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 129349741794 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 15901577 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 15901577 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 15901577 # number of overall misses
+system.cpu.dcache.overall_misses::total 15901577 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 189065481500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 189065481500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 129319032251 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 129319032251 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 113500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 318498003794 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 318498003794 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 318498003794 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 318498003794 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 504107290 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 504107290 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 318384513751 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 318384513751 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 318384513751 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 318384513751 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 504042037 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 504042037 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 91 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 91 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 63 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 63 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 676693337 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 676693337 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 676693337 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 676693337 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021220 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030173 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.032967 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.023503 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.023503 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17681.990108 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24839.592141 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 68 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 68 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 676628084 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 676628084 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 676628084 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 676628084 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021216 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.023501 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.023501 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17679.887499 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24831.987697 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 20025.490931 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20025.490931 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 271743722 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 161500 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 91838 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 2958.946427 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 20187.500000 # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 271440605 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 164500 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 91957 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 2951.821014 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 16450 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3133740 # number of writebacks
-system.cpu.dcache.writebacks::total 3133740 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2967640 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 2967640 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3313508 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3313508 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 3133684 # number of writebacks
+system.cpu.dcache.writebacks::total 3133684 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2964371 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 2964371 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3313808 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3313808 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 6281148 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 6281148 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 6281148 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 6281148 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729587 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7729587 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893894 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1893894 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9623481 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9623481 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9623481 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9623481 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 93074627500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 93074627500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45380366039 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 45380366039 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138454993539 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 138454993539 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138454993539 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 138454993539 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015333 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data 6278179 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 6278179 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 6278179 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 6278179 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729446 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7729446 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893952 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1893952 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9623398 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9623398 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9623398 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9623398 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 93061119500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 93061119500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45369971960 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 45369971960 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138431091460 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 138431091460 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138431091460 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 138431091460 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015335 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12041.345482 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23961.407576 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14387.204956 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14387.204956 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.817537 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23955.185749 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 2953454 # number of replacements
-system.cpu.l2cache.tagsinuse 26874.371014 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 7878176 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 2980778 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 2.642993 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 100977467500 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 10760.004135 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 11.346810 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 16103.020070 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.328369 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.000346 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.491425 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.820141 # Average percentage of cache occupancy
+system.cpu.l2cache.replacements 2953110 # number of replacements
+system.cpu.l2cache.tagsinuse 26875.343151 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7878336 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 2980430 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.643355 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 100989511500 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 10758.137226 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 11.396468 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 16105.809458 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.328312 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.000348 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.491510 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.820170 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 5680110 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 5680139 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 3133740 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 3133740 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 978232 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 978232 # number of ReadExReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 5680299 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 5680328 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 3133684 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 3133684 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 978305 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 978305 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 6658342 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 6658371 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 6658604 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 6658633 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 6658342 # number of overall hits
-system.cpu.l2cache.overall_hits::total 6658371 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 764 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 2049477 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 2050241 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 915662 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 915662 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 764 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 2965139 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 2965903 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 764 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 2965139 # number of overall misses
-system.cpu.l2cache.overall_misses::total 2965903 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26208000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70354429500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 70380637500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31766495000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 31766495000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 26208000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 102120924500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 102147132500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 26208000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 102120924500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 102147132500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 793 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 7729587 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 7730380 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 3133740 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 3133740 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893894 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 1893894 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 793 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 9623481 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 9624274 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 793 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 9623481 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 9624274 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963430 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.265147 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.483481 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963430 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.308115 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963430 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.308115 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34303.664921 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34327.991727 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34692.381031 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34303.664921 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.518471 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34303.664921 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.518471 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 58178500 # number of cycles access was blocked
+system.cpu.l2cache.overall_hits::cpu.data 6658604 # number of overall hits
+system.cpu.l2cache.overall_hits::total 6658633 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 772 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 2049145 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 2049917 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 915649 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 915649 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 772 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 2964794 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 2965566 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 772 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 2964794 # number of overall misses
+system.cpu.l2cache.overall_misses::total 2965566 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26523500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70343968500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 70370492000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31764549000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 31764549000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 26523500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 102108517500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 102135041000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 26523500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 102108517500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 102135041000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 801 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 7729444 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 7730245 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 3133684 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 3133684 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893954 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1893954 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 9623398 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 9624199 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 9623398 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 9624199 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963795 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.265109 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.483459 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963795 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.308082 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963795 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.308082 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34356.865285 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.448450 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34690.748311 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 57329500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 6799 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 6735 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8556.920135 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8512.175204 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 1222459 # number of writebacks
-system.cpu.l2cache.writebacks::total 1222459 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 760 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2049470 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 2050230 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 915662 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 915662 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 760 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 2965132 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 2965892 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 760 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 2965132 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 2965892 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23680000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63915816500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63939496500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28922990000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28922990000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23680000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92838806500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 92862486500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23680000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92838806500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 92862486500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958386 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265146 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483481 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958386 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308114 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958386 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308114 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.894737 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31186.509927 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31586.972049 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.894737 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31310.176579 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.894737 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31310.176579 # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks 1222221 # number of writebacks
+system.cpu.l2cache.writebacks::total 1222221 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 771 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2049137 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 2049908 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 915649 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 915649 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 771 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 2964786 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 2965557 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 771 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 2964786 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 2965557 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24050500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63906561000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63930611500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28918183500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28918183500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24050500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92824744500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 92848795000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24050500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92824744500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 92848795000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265108 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483459 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31193.904021 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31187.061187 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.171225 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 16:28:58
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:48:11
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 861538205000 # Number of ticks simulated
final_tick 861538205000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3009474 # Simulator instruction rate (inst/s)
-host_op_rate 3357290 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1678647401 # Simulator tick rate (ticks/s)
-host_mem_usage 216676 # Number of bytes of host memory used
-host_seconds 513.23 # Real time elapsed on the host
+host_inst_rate 2870592 # Simulator instruction rate (inst/s)
+host_op_rate 3202357 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1601180723 # Simulator tick rate (ticks/s)
+host_mem_usage 213836 # Number of bytes of host memory used
+host_seconds 538.06 # Real time elapsed on the host
sim_insts 1544563049 # Number of instructions simulated
sim_ops 1723073862 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 7759650064 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
system.cpu.num_func_calls 27330134 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 177498450 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
system.cpu.num_int_insts 1536941850 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
system.cpu.num_int_register_reads 7861284536 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 16:33:49
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:53:56
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 2431419954000 # Number of ticks simulated
final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1665877 # Simulator instruction rate (inst/s)
-host_op_rate 1859134 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2632279795 # Simulator tick rate (ticks/s)
-host_mem_usage 225588 # Number of bytes of host memory used
-host_seconds 923.69 # Real time elapsed on the host
+host_inst_rate 1812626 # Simulator instruction rate (inst/s)
+host_op_rate 2022908 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2864161367 # Simulator tick rate (ticks/s)
+host_mem_usage 223004 # Number of bytes of host memory used
+host_seconds 848.91 # Real time elapsed on the host
sim_insts 1538759609 # Number of instructions simulated
sim_ops 1717270343 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 172766016 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
system.cpu.num_func_calls 27330134 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 177498450 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
system.cpu.num_int_insts 1536941850 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:41:00
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 17:57:20
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing
-Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sav
-Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 88752965000 because target called exit()
+122 123 124 Exiting @ tick 76322764500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.088753 # Number of seconds simulated
-sim_ticks 88752965000 # Number of ticks simulated
-final_tick 88752965000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.076323 # Number of seconds simulated
+sim_ticks 76322764500 # Number of ticks simulated
+final_tick 76322764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 137389 # Simulator instruction rate (inst/s)
-host_op_rate 150427 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 70763677 # Simulator tick rate (ticks/s)
-host_mem_usage 230996 # Number of bytes of host memory used
-host_seconds 1254.22 # Real time elapsed on the host
-sim_insts 172315134 # Number of instructions simulated
-sim_ops 188668617 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 245120 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 132800 # Number of instructions bytes read from this memory
+host_inst_rate 160991 # Simulator instruction rate (inst/s)
+host_op_rate 176268 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 71299389 # Simulator tick rate (ticks/s)
+host_mem_usage 228164 # Number of bytes of host memory used
+host_seconds 1070.45 # Real time elapsed on the host
+sim_insts 172333279 # Number of instructions simulated
+sim_ops 188686762 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 246592 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 133376 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 3830 # Number of read requests responded to by this memory
+system.physmem.num_reads 3853 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 2761823 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 1496288 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 2761823 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 3230910 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1747526 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 3230910 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 177505931 # number of cpu cycles simulated
+system.cpu.numCycles 152645530 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 95571520 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 75157417 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 6614903 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 45712904 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 43519744 # Number of BTB hits
+system.cpu.BPredUnit.lookups 97143446 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 76317615 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 6623022 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 46654244 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 44354550 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 4405793 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 115592 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 39981641 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 379098511 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 95571520 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 47925537 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 80419547 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 27360994 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 36321255 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 9619 # Number of stall cycles due to pending traps
+system.cpu.BPredUnit.usedRAS 4440290 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 115738 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 40856932 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 389909160 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 97143446 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 48794840 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 82559996 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 28665024 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 7154273 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 8876 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.CacheLines 36794328 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1674379 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 177448059 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.339145 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.059886 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 37841460 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1897566 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 152586857 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.799629 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.155476 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 97198391 54.78% 54.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 5418485 3.05% 57.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 10378909 5.85% 63.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 10238278 5.77% 69.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 8615978 4.86% 74.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 6776678 3.82% 78.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 6211591 3.50% 81.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 8309244 4.68% 86.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 24300505 13.69% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 70197419 46.00% 46.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 5514909 3.61% 49.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 10699531 7.01% 56.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 10457896 6.85% 63.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 8809329 5.77% 69.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 6861836 4.50% 73.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 6316245 4.14% 77.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 8382546 5.49% 83.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 25347146 16.61% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 177448059 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.538413 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.135695 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 46244696 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 34742594 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 74394013 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1503955 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 20562801 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 14594283 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 162509 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 391670680 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 678477 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 20562801 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 52453090 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 543058 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 28975165 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 69650922 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5263023 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 366605935 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 86833 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 2872425 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 626371131 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1557311065 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1540047768 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 17263297 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 298063520 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 328307611 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2289898 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2280879 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 22663777 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 42181045 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 15903489 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 4032649 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2834648 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 323955475 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2094173 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 249134070 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 566766 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 135834494 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 345192034 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 457957 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 177448059 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.403983 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.631604 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 152586857 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.636399 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.554344 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 46935408 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 5876258 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 76807695 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1114753 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 21852743 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 14847820 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 163458 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 403001894 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 745204 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 21852743 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 52498514 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 705487 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 794640 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 72299255 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4436218 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 380239935 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 319922 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 3547314 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 643715569 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1619843514 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1602242427 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 17601087 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 298092552 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 345623017 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 60567 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 60564 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12828776 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 44110344 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16988908 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 5691426 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 3676812 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 335623795 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 80679 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 253280777 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 910888 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 145778004 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 375851378 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 29413 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 152586857 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.659912 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.759603 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 78553048 44.27% 44.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 28575726 16.10% 60.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 26790293 15.10% 75.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 21442072 12.08% 87.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12420165 7.00% 94.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 5896079 3.32% 97.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 3065113 1.73% 99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 544695 0.31% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 160868 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 58969897 38.65% 38.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 23051369 15.11% 53.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 25143684 16.48% 70.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 20551680 13.47% 83.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12918795 8.47% 92.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 6596322 4.32% 96.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 4048422 2.65% 99.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1113826 0.73% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 192862 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 177448059 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 152586857 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 586662 26.53% 26.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5526 0.25% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 139 0.01% 26.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 26 0.00% 26.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1170221 52.93% 79.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 448459 20.28% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 968336 37.79% 37.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5589 0.22% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 91 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 33 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1185185 46.25% 84.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 403164 15.73% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 194883965 78.22% 78.22% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 995226 0.40% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 33040 0.01% 78.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 164177 0.07% 78.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 253566 0.10% 78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 76466 0.03% 78.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 466502 0.19% 79.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 206303 0.08% 79.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 71862 0.03% 79.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 38048843 15.27% 94.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 13933800 5.59% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 197697657 78.05% 78.05% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 995408 0.39% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 33135 0.01% 78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 164107 0.06% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 254969 0.10% 78.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 76438 0.03% 78.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 467546 0.18% 78.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 206313 0.08% 78.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 71855 0.03% 78.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.95% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 39090450 15.43% 94.38% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 14222579 5.62% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 249134070 # Type of FU issued
-system.cpu.iq.rate 1.403525 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2211033 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.008875 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 674734020 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 459694658 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 237377529 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 3759978 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2202441 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 1840495 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 249450810 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1894293 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1632018 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 253280777 # Type of FU issued
+system.cpu.iq.rate 1.659274 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2562398 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010117 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 658846824 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 479250938 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 240868765 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 3774873 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 2250330 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 1852271 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 253948063 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1895112 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 2034666 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 12329139 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 16500 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 13400 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 3256434 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 14254809 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 18806 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 19550 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 4338224 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 152 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 46 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 20562801 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 11850 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 518 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 326106294 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1027766 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 42181045 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 15903489 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2071684 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 91 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 257 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 13400 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4154974 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 3938016 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8092990 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 242315384 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 36530974 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 6818686 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 21852743 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 13300 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 608 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 335763367 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 963800 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 44110344 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 16988908 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 58117 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 150 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 281 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 19550 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4170846 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 3956659 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8127505 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 246138856 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 37439094 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 7141921 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 56646 # number of nop insts executed
-system.cpu.iew.exec_refs 50147755 # number of memory reference insts executed
-system.cpu.iew.exec_branches 53661515 # Number of branches executed
-system.cpu.iew.exec_stores 13616781 # Number of stores executed
-system.cpu.iew.exec_rate 1.365111 # Inst execution rate
-system.cpu.iew.wb_sent 240126243 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 239218024 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 143974107 # num instructions producing a value
-system.cpu.iew.wb_consumers 250982237 # num instructions consuming a value
+system.cpu.iew.exec_nop 58893 # number of nop insts executed
+system.cpu.iew.exec_refs 51255438 # number of memory reference insts executed
+system.cpu.iew.exec_branches 54101167 # Number of branches executed
+system.cpu.iew.exec_stores 13816344 # Number of stores executed
+system.cpu.iew.exec_rate 1.612486 # Inst execution rate
+system.cpu.iew.wb_sent 243866975 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 242721036 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 150184249 # num instructions producing a value
+system.cpu.iew.wb_consumers 269391648 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.347662 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.573643 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.590096 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.557494 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 172329522 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 188683005 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 137423310 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1636216 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 6480810 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 156885259 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.202682 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.914186 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 172347667 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 188701150 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 147062192 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 51266 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 6488296 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 130734115 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.443396 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.157229 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 79822518 50.88% 50.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 37410215 23.85% 74.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 15894720 10.13% 84.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 8464339 5.40% 90.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 4786654 3.05% 93.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1458057 0.93% 94.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1746360 1.11% 95.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1243896 0.79% 96.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6058500 3.86% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 60440090 46.23% 46.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 32094015 24.55% 70.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 14011020 10.72% 81.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 7691837 5.88% 87.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 4423613 3.38% 90.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1340820 1.03% 91.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1731909 1.32% 93.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1286910 0.98% 94.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 7713901 5.90% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 156885259 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 172329522 # Number of instructions committed
-system.cpu.commit.committedOps 188683005 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 130734115 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 172347667 # Number of instructions committed
+system.cpu.commit.committedOps 188701150 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 42498961 # Number of memory references committed
-system.cpu.commit.loads 29851906 # Number of loads committed
+system.cpu.commit.refs 42506219 # Number of memory references committed
+system.cpu.commit.loads 29855535 # Number of loads committed
system.cpu.commit.membars 22408 # Number of memory barriers committed
-system.cpu.commit.branches 40284104 # Number of branches committed
+system.cpu.commit.branches 40287733 # Number of branches committed
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 150115909 # Number of committed integer instructions.
+system.cpu.commit.int_insts 150130425 # Number of committed integer instructions.
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 6058500 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 7713901 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 476927873 # The number of ROB reads
-system.cpu.rob.rob_writes 672877067 # The number of ROB writes
-system.cpu.timesIdled 1694 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 57872 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 172315134 # Number of Instructions Simulated
-system.cpu.committedOps 188668617 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 172315134 # Number of Instructions Simulated
-system.cpu.cpi 1.030124 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.030124 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.970757 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.970757 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1076172941 # number of integer regfile reads
-system.cpu.int_regfile_writes 384809064 # number of integer regfile writes
-system.cpu.fp_regfile_reads 2908130 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2493684 # number of floating regfile writes
-system.cpu.misc_regfile_reads 462718931 # number of misc regfile reads
-system.cpu.misc_regfile_writes 824878 # number of misc regfile writes
-system.cpu.icache.replacements 2566 # number of replacements
-system.cpu.icache.tagsinuse 1372.206162 # Cycle average of tags in use
-system.cpu.icache.total_refs 36789295 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 4311 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 8533.819299 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 458778355 # The number of ROB reads
+system.cpu.rob.rob_writes 693498788 # The number of ROB writes
+system.cpu.timesIdled 1746 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 58673 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 172333279 # Number of Instructions Simulated
+system.cpu.committedOps 188686762 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 172333279 # Number of Instructions Simulated
+system.cpu.cpi 0.885758 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.885758 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.128977 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.128977 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1093182861 # number of integer regfile reads
+system.cpu.int_regfile_writes 388952433 # number of integer regfile writes
+system.cpu.fp_regfile_reads 2911975 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2511798 # number of floating regfile writes
+system.cpu.misc_regfile_reads 476343702 # number of misc regfile reads
+system.cpu.misc_regfile_writes 832136 # number of misc regfile writes
+system.cpu.icache.replacements 2645 # number of replacements
+system.cpu.icache.tagsinuse 1374.603363 # Cycle average of tags in use
+system.cpu.icache.total_refs 37836261 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 4394 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 8610.892353 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1372.206162 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.670023 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.670023 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 36789295 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 36789295 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 36789295 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 36789295 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 36789295 # number of overall hits
-system.cpu.icache.overall_hits::total 36789295 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 5033 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 5033 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 5033 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 5033 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 5033 # number of overall misses
-system.cpu.icache.overall_misses::total 5033 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 109886500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 109886500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 109886500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 109886500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 109886500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 109886500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 36794328 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 36794328 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 36794328 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 36794328 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 36794328 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 36794328 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 1374.603363 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.671193 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.671193 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 37836261 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 37836261 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 37836261 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 37836261 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 37836261 # number of overall hits
+system.cpu.icache.overall_hits::total 37836261 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 5199 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 5199 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 5199 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 5199 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 5199 # number of overall misses
+system.cpu.icache.overall_misses::total 5199 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 112756500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 112756500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 112756500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 112756500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 112756500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 112756500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 37841460 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 37841460 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 37841460 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 37841460 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 37841460 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 37841460 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000137 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000137 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21833.200874 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 21833.200874 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21833.200874 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21688.113099 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 722 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 722 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 722 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 722 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 722 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 722 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4311 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 4311 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 4311 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 4311 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 4311 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 4311 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78475000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 78475000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78475000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 78475000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78475000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 78475000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18203.433078 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18203.433078 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18203.433078 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 804 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 804 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 804 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 804 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 804 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 804 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4395 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 4395 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 4395 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 4395 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 4395 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 4395 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78893000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 78893000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78893000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 78893000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78893000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 78893000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17950.625711 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 57 # number of replacements
-system.cpu.dcache.tagsinuse 1411.383328 # Cycle average of tags in use
-system.cpu.dcache.total_refs 46835892 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1864 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 25126.551502 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 59 # number of replacements
+system.cpu.dcache.tagsinuse 1421.643782 # Cycle average of tags in use
+system.cpu.dcache.total_refs 47334662 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1881 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 25164.626263 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1411.383328 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.344576 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.344576 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 34426629 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 34426629 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 12356789 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 12356789 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 27646 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 27646 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 24828 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 24828 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 46783418 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 46783418 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 46783418 # number of overall hits
-system.cpu.dcache.overall_hits::total 46783418 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1806 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1806 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 7498 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 7498 # number of WriteReq misses
+system.cpu.dcache.occ_blocks::cpu.data 1421.643782 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.347081 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.347081 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 34919209 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 34919209 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 12356677 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 12356677 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 30319 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 30319 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 28457 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 28457 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 47275886 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 47275886 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 47275886 # number of overall hits
+system.cpu.dcache.overall_hits::total 47275886 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1860 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1860 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 7610 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 7610 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 9304 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9304 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9304 # number of overall misses
-system.cpu.dcache.overall_misses::total 9304 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 59300000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 59300000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 235066000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 235066000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 9470 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 9470 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 9470 # number of overall misses
+system.cpu.dcache.overall_misses::total 9470 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 60591000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 60591000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 237329500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 237329500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 64000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 64000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 294366000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 294366000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 294366000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 294366000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 34428435 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 34428435 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 297920500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 297920500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 297920500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 297920500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 34921069 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 34921069 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 27648 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 27648 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 24828 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 24828 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 46792722 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 46792722 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 46792722 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 46792722 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000052 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000606 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000072 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000199 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000199 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32834.994463 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31350.493465 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30321 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 30321 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 28457 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 28457 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 47285356 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 47285356 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 47285356 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 47285356 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000615 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000200 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000200 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32575.806452 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31186.530880 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31638.650043 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31638.650043 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 19500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 9750 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 20 # number of writebacks
-system.cpu.dcache.writebacks::total 20 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1032 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1032 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6408 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 6408 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
+system.cpu.dcache.writebacks::total 18 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1056 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 1056 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6533 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 6533 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7440 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7440 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7440 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7440 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1090 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1090 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1864 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1864 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1864 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1864 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24612000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 24612000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38340000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 38340000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62952000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 62952000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62952000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 62952000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data 7589 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7589 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7589 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7589 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 804 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 804 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1881 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1881 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1881 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1881 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25610500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 25610500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 37862500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 37862500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63473000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 63473000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63473000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 63473000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31798.449612 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35174.311927 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33772.532189 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33772.532189 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31853.855721 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35155.524605 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 1984.437698 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2319 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 2759 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.840522 # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 2017.739485 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2396 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 2793 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.857859 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 4.039076 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 1445.465976 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 534.932646 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.044112 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.016325 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.060560 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 2233 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 85 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2318 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 20 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 20 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 2233 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 93 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2326 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 2233 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 93 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2326 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 2078 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 689 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 2767 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 1082 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 1082 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 2078 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 1771 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 3849 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 2078 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 1771 # number of overall misses
-system.cpu.l2cache.overall_misses::total 3849 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71213500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23628000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 94841500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37178000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 37178000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 71213500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 60806000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 132019500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 71213500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 60806000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 132019500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 4311 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 774 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 5085 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 20 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 20 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 1090 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 1090 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 4311 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1864 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 6175 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 4311 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1864 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 6175 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.482023 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890181 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992661 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.482023 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.950107 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.482023 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.950107 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34270.211742 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34293.178520 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34360.443623 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34270.211742 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34334.274421 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34270.211742 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34334.274421 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 4.002094 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 1457.512395 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 556.224996 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.044480 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.016975 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.061577 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 2308 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 2396 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 2308 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2405 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 2308 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2405 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 2087 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 716 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 2803 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 1068 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 1068 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 2087 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 1784 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 3871 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 2087 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 1784 # number of overall misses
+system.cpu.l2cache.overall_misses::total 3871 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71492500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24574000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 96066500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36706000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 36706000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 71492500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 61280000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 132772500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 71492500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 61280000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 132772500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 4395 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 804 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 5199 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1077 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1077 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 4395 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1881 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 6276 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 4395 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1881 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 6276 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.474858 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890547 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991643 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.474858 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.948432 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.474858 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.948432 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.109248 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34321.229050 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.913858 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 16 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 16 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 16 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 19 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2075 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 673 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 2748 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1082 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 1082 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 2075 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 1755 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 3830 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 2075 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1755 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 3830 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64436000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20976000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85412000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33589000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33589000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64436000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54565000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 119001000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64436000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54565000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 119001000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.481327 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869509 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992661 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.481327 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941524 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.481327 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941524 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31053.493976 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31167.904903 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31043.438078 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31053.493976 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31091.168091 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31053.493976 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31091.168091 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 18 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2084 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 701 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 2785 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1068 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1068 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2084 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1769 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 3853 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2084 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1769 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 3853 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64692000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21857000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 86549000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33156000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33156000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64692000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 55013000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 119705000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64692000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 55013000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 119705000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871891 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991643 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31042.226488 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31179.743224 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.943820 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 16:37:27
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 18:08:16
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 103106771000 # Number of ticks simulated
final_tick 103106771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3116971 # Simulator instruction rate (inst/s)
-host_op_rate 3412781 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1865050079 # Simulator tick rate (ticks/s)
-host_mem_usage 219792 # Number of bytes of host memory used
-host_seconds 55.28 # Real time elapsed on the host
+host_inst_rate 2490166 # Simulator instruction rate (inst/s)
+host_op_rate 2726490 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1489999442 # Simulator tick rate (ticks/s)
+host_mem_usage 216948 # Number of bytes of host memory used
+host_seconds 69.20 # Real time elapsed on the host
sim_insts 172317417 # Number of instructions simulated
sim_ops 188670900 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 869973902 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
system.cpu.num_func_calls 3504894 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 32534025 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 32493891 # number of instructions that are conditional controls
system.cpu.num_int_insts 150106226 # number of integer instructions
system.cpu.num_fp_insts 1752310 # number of float instructions
system.cpu.num_int_register_reads 809396650 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 16:38:33
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 18:09:36
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 232077154000 # Number of ticks simulated
final_tick 232077154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1962361 # Simulator instruction rate (inst/s)
-host_op_rate 2148995 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2650211347 # Simulator tick rate (ticks/s)
-host_mem_usage 228700 # Number of bytes of host memory used
-host_seconds 87.57 # Real time elapsed on the host
+host_inst_rate 1841932 # Simulator instruction rate (inst/s)
+host_op_rate 2017113 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2487570299 # Simulator tick rate (ticks/s)
+host_mem_usage 226116 # Number of bytes of host memory used
+host_seconds 93.29 # Real time elapsed on the host
sim_insts 171842491 # Number of instructions simulated
sim_ops 188185929 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 220992 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
system.cpu.num_func_calls 3504894 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 32534025 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 32493891 # number of instructions that are conditional controls
system.cpu.num_int_insts 150106226 # number of integer instructions
system.cpu.num_fp_insts 1752310 # number of float instructions
system.cpu.num_int_register_reads 898652287 # number of times the integer registers were read
header_cycles=1
use_default_range=false
width=64
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
max_mem_size=268435456
mem_start_addr=0
system=system
pio=system.iobus.master[1]
-[system.realview.rtc_fake]
-type=AmbaFake
-amba_id=266289
-ignore_access=false
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+gic=system.realview.gic
+int_delay=100000
+int_num=42
pio_addr=268529664
pio_latency=1000
system=system
+time=Thu Jan 1 00:00:00 2009
pio=system.iobus.master[23]
[system.realview.sci_fake]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 08:32:03
-gem5 started Mar 9 2012 08:33:32
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 16:34:57
gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
-The currently selected ARM platforms doesn't support
- the amount of DRAM you've selected. Please try
- another platform
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
sim_ticks 2411694099500 # Number of ticks simulated
final_tick 2411694099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2022463 # Simulator instruction rate (inst/s)
-host_op_rate 2614492 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 79249307765 # Simulator tick rate (ticks/s)
-host_mem_usage 379912 # Number of bytes of host memory used
-host_seconds 30.43 # Real time elapsed on the host
-sim_insts 61546998 # Number of instructions simulated
-sim_ops 79563488 # Number of ops (including micro ops) simulated
+host_inst_rate 2019241 # Simulator instruction rate (inst/s)
+host_op_rate 2610327 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 79123006525 # Simulator tick rate (ticks/s)
+host_mem_usage 377328 # Number of bytes of host memory used
+host_seconds 30.48 # Real time elapsed on the host
+sim_insts 61547057 # Number of instructions simulated
+sim_ops 79563547 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.bw_write 4223269 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 55336844 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 127720 # number of replacements
-system.l2c.tagsinuse 25547.920863 # Cycle average of tags in use
-system.l2c.total_refs 1498989 # Total number of references to valid blocks.
+system.l2c.tagsinuse 25547.920882 # Cycle average of tags in use
+system.l2c.total_refs 1498993 # Total number of references to valid blocks.
system.l2c.sampled_refs 156132 # Sample count of references to valid blocks.
-system.l2c.avg_refs 9.600780 # Average number of references to valid blocks.
+system.l2c.avg_refs 9.600806 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 14919.913596 # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks 14919.913613 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 1.146267 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.046172 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 3116.154269 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 1287.935030 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 3116.154275 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 1287.935036 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 4.789000 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.itb.walker 0.017808 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 2080.961375 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 4136.957345 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 2080.961372 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 4136.957340 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.227660 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000017 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.data 213171 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 4123 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 1590 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 368109 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 131706 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1218925 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 580461 # number of Writeback hits
-system.l2c.Writeback_hits::total 580461 # number of Writeback hits
+system.l2c.ReadReq_hits::cpu1.inst 368111 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 131707 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1218928 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 580462 # number of Writeback hits
+system.l2c.Writeback_hits::total 580462 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 776 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 523 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 1299 # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.data 278002 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 4123 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 1590 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 368109 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 169503 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1321553 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 368111 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 169504 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1321556 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 5051 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 2156 # number of overall hits
system.l2c.overall_hits::cpu0.inst 493019 # number of overall hits
system.l2c.overall_hits::cpu0.data 278002 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 4123 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 1590 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 368109 # number of overall hits
-system.l2c.overall_hits::cpu1.data 169503 # number of overall hits
-system.l2c.overall_hits::total 1321553 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 368111 # number of overall hits
+system.l2c.overall_hits::cpu1.data 169504 # number of overall hits
+system.l2c.overall_hits::total 1321556 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 7 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 10289 # number of ReadReq misses
system.l2c.ReadReq_accesses::cpu0.data 222557 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 4144 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 1603 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 373203 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 141836 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1253876 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 580461 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 580461 # number of Writeback accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 373205 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 141837 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1253879 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 580462 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 580462 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 7125 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 4015 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 11140 # number of UpgradeReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.data 386436 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 4144 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 1603 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 373203 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 228418 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1504337 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 373205 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 228419 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1504340 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 5062 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 2163 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 503308 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 386436 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 4144 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 1603 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 373203 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 228418 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1504337 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 373205 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 228419 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1504340 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002173 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.003236 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.020443 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.005068 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.008110 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.013649 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.071421 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.071420 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.891088 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.869738 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843284 # miss rate for SCUpgradeReq accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.005068 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.008110 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.013649 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.257926 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.257925 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002173 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.003236 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.020443 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.005068 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.008110 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.013649 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.257926 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.257925 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 9339288 # DTB read hits
+system.cpu0.dtb.read_hits 9339290 # DTB read hits
system.cpu0.dtb.read_misses 5153 # DTB read misses
-system.cpu0.dtb.write_hits 6907876 # DTB write hits
+system.cpu0.dtb.write_hits 6907877 # DTB write hits
system.cpu0.dtb.write_misses 1048 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 9344441 # DTB read accesses
-system.cpu0.dtb.write_accesses 6908924 # DTB write accesses
+system.cpu0.dtb.read_accesses 9344443 # DTB read accesses
+system.cpu0.dtb.write_accesses 6908925 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 16247164 # DTB hits
+system.cpu0.dtb.hits 16247167 # DTB hits
system.cpu0.dtb.misses 6201 # DTB misses
-system.cpu0.dtb.accesses 16253365 # DTB accesses
-system.cpu0.itb.inst_hits 34822552 # ITB inst hits
+system.cpu0.dtb.accesses 16253368 # DTB accesses
+system.cpu0.itb.inst_hits 34822572 # ITB inst hits
system.cpu0.itb.inst_misses 2978 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 34825530 # ITB inst accesses
-system.cpu0.itb.hits 34822552 # DTB hits
+system.cpu0.itb.inst_accesses 34825550 # ITB inst accesses
+system.cpu0.itb.hits 34822572 # DTB hits
system.cpu0.itb.misses 2978 # DTB misses
-system.cpu0.itb.accesses 34825530 # DTB accesses
+system.cpu0.itb.accesses 34825550 # DTB accesses
system.cpu0.numCycles 4823340800 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 34068103 # Number of instructions committed
-system.cpu0.committedOps 44975797 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 39858123 # Number of integer alu accesses
+system.cpu0.committedInsts 34068123 # Number of instructions committed
+system.cpu0.committedOps 44975817 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 39858141 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 4945 # Number of float alu accesses
system.cpu0.num_func_calls 1311755 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4652122 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 39858123 # number of integer instructions
+system.cpu0.num_conditional_control_insts 4519198 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 39858141 # number of integer instructions
system.cpu0.num_fp_insts 4945 # number of float instructions
-system.cpu0.num_int_register_reads 202125744 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 42204131 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 202125837 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 42204153 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3641 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1308 # number of times the floating registers were written
-system.cpu0.num_mem_refs 17030946 # number of memory refs
-system.cpu0.num_load_insts 9786549 # Number of load instructions
-system.cpu0.num_store_insts 7244397 # Number of store instructions
-system.cpu0.num_idle_cycles 4777543068.852608 # Number of idle cycles
-system.cpu0.num_busy_cycles 45797731.147393 # Number of busy cycles
+system.cpu0.num_mem_refs 17030949 # number of memory refs
+system.cpu0.num_load_insts 9786551 # Number of load instructions
+system.cpu0.num_store_insts 7244398 # Number of store instructions
+system.cpu0.num_idle_cycles 4777543048.852804 # Number of idle cycles
+system.cpu0.num_busy_cycles 45797751.147196 # Number of busy cycles
system.cpu0.not_idle_fraction 0.009495 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.990505 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 59311 # number of quiesce instructions executed
system.cpu0.icache.replacements 504460 # number of replacements
system.cpu0.icache.tagsinuse 511.627588 # Cycle average of tags in use
-system.cpu0.icache.total_refs 34319155 # Total number of references to valid blocks.
+system.cpu0.icache.total_refs 34319175 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 504972 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 67.962491 # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs 67.962531 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 64519524000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 511.627588 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.999273 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.999273 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 34319155 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 34319155 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 34319155 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 34319155 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 34319155 # number of overall hits
-system.cpu0.icache.overall_hits::total 34319155 # number of overall hits
+system.cpu0.icache.ReadReq_hits::cpu0.inst 34319175 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 34319175 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 34319175 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 34319175 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 34319175 # number of overall hits
+system.cpu0.icache.overall_hits::total 34319175 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 504973 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 504973 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 504973 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 504973 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 504973 # number of overall misses
system.cpu0.icache.overall_misses::total 504973 # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 34824128 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 34824128 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 34824128 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 34824128 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 34824128 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 34824128 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 34824148 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 34824148 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 34824148 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 34824148 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 34824148 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 34824148 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014501 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014501 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014501 # miss rate for overall accesses
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 380107 # number of replacements
system.cpu0.dcache.tagsinuse 479.716402 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 14708286 # Total number of references to valid blocks.
+system.cpu0.dcache.total_refs 14708289 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 380619 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 38.643068 # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs 38.643076 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 479.716402 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.936946 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.936946 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 7803296 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 7803296 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 6534059 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 6534059 # number of WriteReq hits
+system.cpu0.dcache.ReadReq_hits::cpu0.data 7803298 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 7803298 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 6534060 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 6534060 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172314 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 172314 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 174866 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 174866 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 14337355 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 14337355 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 14337355 # number of overall hits
-system.cpu0.dcache.overall_hits::total 14337355 # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data 14337358 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 14337358 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 14337358 # number of overall hits
+system.cpu0.dcache.overall_hits::total 14337358 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 237350 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 237350 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 183580 # number of WriteReq misses
system.cpu0.dcache.demand_misses::total 420930 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 420930 # number of overall misses
system.cpu0.dcache.overall_misses::total 420930 # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 8040646 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 8040646 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 6717639 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 6717639 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 8040648 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 8040648 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 6717640 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 6717640 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182192 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 182192 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182159 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 182159 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 14758285 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 14758285 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 14758285 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 14758285 # number of overall (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data 14758288 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 14758288 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 14758288 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 14758288 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029519 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027328 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054218 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 6258230 # DTB read hits
+system.cpu1.dtb.read_hits 6258240 # DTB read hits
system.cpu1.dtb.read_misses 2159 # DTB read misses
-system.cpu1.dtb.write_hits 4713962 # DTB write hits
+system.cpu1.dtb.write_hits 4713968 # DTB write hits
system.cpu1.dtb.write_misses 1181 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.prefetch_faults 92 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 6260389 # DTB read accesses
-system.cpu1.dtb.write_accesses 4715143 # DTB write accesses
+system.cpu1.dtb.read_accesses 6260399 # DTB read accesses
+system.cpu1.dtb.write_accesses 4715149 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 10972192 # DTB hits
+system.cpu1.dtb.hits 10972208 # DTB hits
system.cpu1.dtb.misses 3340 # DTB misses
-system.cpu1.dtb.accesses 10975532 # DTB accesses
-system.cpu1.itb.inst_hits 27739434 # ITB inst hits
+system.cpu1.dtb.accesses 10975548 # DTB accesses
+system.cpu1.itb.inst_hits 27739473 # ITB inst hits
system.cpu1.itb.inst_misses 1388 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 27740822 # ITB inst accesses
-system.cpu1.itb.hits 27739434 # DTB hits
+system.cpu1.itb.inst_accesses 27740861 # ITB inst accesses
+system.cpu1.itb.hits 27739473 # DTB hits
system.cpu1.itb.misses 1388 # DTB misses
-system.cpu1.itb.accesses 27740822 # DTB accesses
+system.cpu1.itb.accesses 27740861 # DTB accesses
system.cpu1.numCycles 4822838236 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 27478895 # Number of instructions committed
-system.cpu1.committedOps 34587691 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 30998246 # Number of integer alu accesses
+system.cpu1.committedInsts 27478934 # Number of instructions committed
+system.cpu1.committedOps 34587730 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 30998282 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 5772 # Number of float alu accesses
system.cpu1.num_func_calls 758024 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3438794 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 30998246 # number of integer instructions
+system.cpu1.num_conditional_control_insts 3403316 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 30998282 # number of integer instructions
system.cpu1.num_fp_insts 5772 # number of float instructions
-system.cpu1.num_int_register_reads 156835040 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 33469179 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 156835224 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 33469234 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 3980 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1792 # number of times the floating registers were written
-system.cpu1.num_mem_refs 11415835 # number of memory refs
-system.cpu1.num_load_insts 6478994 # Number of load instructions
-system.cpu1.num_store_insts 4936841 # Number of store instructions
-system.cpu1.num_idle_cycles 4787960178.177661 # Number of idle cycles
-system.cpu1.num_busy_cycles 34878057.822339 # Number of busy cycles
+system.cpu1.num_mem_refs 11415851 # number of memory refs
+system.cpu1.num_load_insts 6479004 # Number of load instructions
+system.cpu1.num_store_insts 4936847 # Number of store instructions
+system.cpu1.num_idle_cycles 4787960139.182108 # Number of idle cycles
+system.cpu1.num_busy_cycles 34878096.817892 # Number of busy cycles
system.cpu1.not_idle_fraction 0.007232 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.992768 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 33011 # number of quiesce instructions executed
-system.cpu1.icache.replacements 374406 # number of replacements
+system.cpu1.icache.replacements 374408 # number of replacements
system.cpu1.icache.tagsinuse 498.143079 # Cycle average of tags in use
-system.cpu1.icache.total_refs 27365572 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 374918 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 72.990819 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 69956143000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.total_refs 27365609 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 374920 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 72.990529 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 69956153000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 498.143079 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.972936 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.972936 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 27365572 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 27365572 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 27365572 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 27365572 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 27365572 # number of overall hits
-system.cpu1.icache.overall_hits::total 27365572 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 374920 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 374920 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 374920 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 374920 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 374920 # number of overall misses
-system.cpu1.icache.overall_misses::total 374920 # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 27740492 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 27740492 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 27740492 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 27740492 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 27740492 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 27740492 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst 27365609 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 27365609 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 27365609 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 27365609 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 27365609 # number of overall hits
+system.cpu1.icache.overall_hits::total 27365609 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 374922 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 374922 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 374922 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 374922 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 374922 # number of overall misses
+system.cpu1.icache.overall_misses::total 374922 # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 27740531 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 27740531 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 27740531 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 27740531 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 27740531 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 27740531 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013515 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013515 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013515 # miss rate for overall accesses
system.cpu1.icache.writebacks::writebacks 13905 # number of writebacks
system.cpu1.icache.writebacks::total 13905 # number of writebacks
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 247434 # number of replacements
-system.cpu1.dcache.tagsinuse 444.903488 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 9876826 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 247805 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 39.857251 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 69253206000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 444.903488 # Average occupied blocks per requestor
+system.cpu1.dcache.replacements 247435 # number of replacements
+system.cpu1.dcache.tagsinuse 444.903487 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 9876841 # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs 247806 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 39.857150 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 69253216000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data 444.903487 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.868952 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.868952 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 5955973 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 5955973 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 3777038 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 3777038 # number of WriteReq hits
+system.cpu1.dcache.ReadReq_hits::cpu1.data 5955982 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 5955982 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 3777044 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 3777044 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 59593 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 59593 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 60090 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 60090 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 9733011 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 9733011 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 9733011 # number of overall hits
-system.cpu1.dcache.overall_hits::total 9733011 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 165799 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 165799 # number of ReadReq misses
+system.cpu1.dcache.demand_hits::cpu1.data 9733026 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 9733026 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 9733026 # number of overall hits
+system.cpu1.dcache.overall_hits::total 9733026 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 165800 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 165800 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 111467 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 111467 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10725 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 10725 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10198 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 10198 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 277266 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 277266 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 277266 # number of overall misses
-system.cpu1.dcache.overall_misses::total 277266 # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 6121772 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 6121772 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 3888505 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 3888505 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.demand_misses::cpu1.data 277267 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 277267 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 277267 # number of overall misses
+system.cpu1.dcache.overall_misses::total 277267 # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 6121782 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 6121782 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 3888511 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 3888511 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 70318 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 70318 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 70288 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 70288 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 10010277 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 10010277 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 10010277 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 10010277 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027083 # miss rate for ReadReq accesses
+system.cpu1.dcache.demand_accesses::cpu1.data 10010293 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 10010293 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 10010293 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 10010293 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027084 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028666 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152521 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.145089 # miss rate for StoreCondReq accesses
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 202201 # number of writebacks
-system.cpu1.dcache.writebacks::total 202201 # number of writebacks
+system.cpu1.dcache.writebacks::writebacks 202202 # number of writebacks
+system.cpu1.dcache.writebacks::total 202202 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
header_cycles=1
use_default_range=false
width=64
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
max_mem_size=268435456
mem_start_addr=0
system=system
pio=system.iobus.master[1]
-[system.realview.rtc_fake]
-type=AmbaFake
-amba_id=266289
-ignore_access=false
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+gic=system.realview.gic
+int_delay=100000
+int_num=42
pio_addr=268529664
pio_latency=1000
system=system
+time=Thu Jan 1 00:00:00 2009
pio=system.iobus.master[23]
[system.realview.sci_fake]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 08:32:03
-gem5 started Mar 9 2012 08:33:32
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 16:34:16
gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
-The currently selected ARM platforms doesn't support
- the amount of DRAM you've selected. Please try
- another platform
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
sim_ticks 2332316587000 # Number of ticks simulated
final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1979884 # Simulator instruction rate (inst/s)
-host_op_rate 2556849 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 77919104565 # Simulator tick rate (ticks/s)
-host_mem_usage 379864 # Number of bytes of host memory used
-host_seconds 29.93 # Real time elapsed on the host
-sim_insts 59262876 # Number of instructions simulated
-sim_ops 76532931 # Number of ops (including micro ops) simulated
+host_inst_rate 1994377 # Simulator instruction rate (inst/s)
+host_op_rate 2575566 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 78489486028 # Simulator tick rate (ticks/s)
+host_mem_usage 377288 # Number of bytes of host memory used
+host_seconds 29.72 # Real time elapsed on the host
+sim_insts 59262896 # Number of instructions simulated
+sim_ops 76532951 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.bw_write 4106561 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 56699565 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 116822 # number of replacements
-system.l2c.tagsinuse 24240.388378 # Cycle average of tags in use
+system.l2c.tagsinuse 24240.388395 # Cycle average of tags in use
system.l2c.total_refs 1520830 # Total number of references to valid blocks.
system.l2c.sampled_refs 146847 # Sample count of references to valid blocks.
system.l2c.avg_refs 10.356562 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 13639.466210 # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks 13639.466229 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker 7.864412 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker 1.966419 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst 5246.411267 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data 5344.680069 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data 5344.680068 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.208122 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 14940566 # DTB read hits
+system.cpu.dtb.read_hits 14940568 # DTB read hits
system.cpu.dtb.read_misses 7288 # DTB read misses
-system.cpu.dtb.write_hits 11198205 # DTB write hits
+system.cpu.dtb.write_hits 11198206 # DTB write hits
system.cpu.dtb.write_misses 2199 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 14947854 # DTB read accesses
-system.cpu.dtb.write_accesses 11200404 # DTB write accesses
+system.cpu.dtb.read_accesses 14947856 # DTB read accesses
+system.cpu.dtb.write_accesses 11200405 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 26138771 # DTB hits
+system.cpu.dtb.hits 26138774 # DTB hits
system.cpu.dtb.misses 9487 # DTB misses
-system.cpu.dtb.accesses 26148258 # DTB accesses
-system.cpu.itb.inst_hits 60273889 # ITB inst hits
+system.cpu.dtb.accesses 26148261 # DTB accesses
+system.cpu.itb.inst_hits 60273909 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 60278360 # ITB inst accesses
-system.cpu.itb.hits 60273889 # DTB hits
+system.cpu.itb.inst_accesses 60278380 # ITB inst accesses
+system.cpu.itb.hits 60273909 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
-system.cpu.itb.accesses 60278360 # DTB accesses
+system.cpu.itb.accesses 60278380 # DTB accesses
system.cpu.numCycles 4664556206 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 59262876 # Number of instructions committed
-system.cpu.committedOps 76532931 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 68161177 # Number of integer alu accesses
+system.cpu.committedInsts 59262896 # Number of instructions committed
+system.cpu.committedOps 76532951 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 68161195 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
system.cpu.num_func_calls 1971944 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7793824 # number of instructions that are conditional controls
-system.cpu.num_int_insts 68161177 # number of integer instructions
+system.cpu.num_conditional_control_insts 7636089 # number of instructions that are conditional controls
+system.cpu.num_int_insts 68161195 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
-system.cpu.num_int_register_reads 345365607 # number of times the integer registers were read
-system.cpu.num_int_register_writes 72877692 # number of times the integer registers were written
+system.cpu.num_int_register_reads 345365700 # number of times the integer registers were read
+system.cpu.num_int_register_writes 72877714 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
-system.cpu.num_mem_refs 27310784 # number of memory refs
-system.cpu.num_load_insts 15607074 # Number of load instructions
-system.cpu.num_store_insts 11703710 # Number of store instructions
-system.cpu.num_idle_cycles 4586920150.977920 # Number of idle cycles
-system.cpu.num_busy_cycles 77636055.022080 # Number of busy cycles
+system.cpu.num_mem_refs 27310787 # number of memory refs
+system.cpu.num_load_insts 15607076 # Number of load instructions
+system.cpu.num_store_insts 11703711 # Number of store instructions
+system.cpu.num_idle_cycles 4586920130.978250 # Number of idle cycles
+system.cpu.num_busy_cycles 77636075.021750 # Number of busy cycles
system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.983356 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 82751 # number of quiesce instructions executed
system.cpu.icache.replacements 847054 # number of replacements
system.cpu.icache.tagsinuse 511.678552 # Cycle average of tags in use
-system.cpu.icache.total_refs 59429083 # Total number of references to valid blocks.
+system.cpu.icache.total_refs 59429103 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 70.117351 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 5705452000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.avg_refs 70.117375 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 5705462000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 511.678552 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 59429083 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 59429083 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 59429083 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 59429083 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 59429083 # number of overall hits
-system.cpu.icache.overall_hits::total 59429083 # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst 59429103 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 59429103 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 59429103 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 59429103 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 59429103 # number of overall hits
+system.cpu.icache.overall_hits::total 59429103 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 847566 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 847566 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 847566 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 847566 # number of overall misses
system.cpu.icache.overall_misses::total 847566 # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst 60276649 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 60276649 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 60276649 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 60276649 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 60276649 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 60276649 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst 60276669 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 60276669 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 60276669 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 60276669 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 60276669 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 60276669 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014061 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.014061 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.014061 # miss rate for overall accesses
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 622134 # number of replacements
system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use
-system.cpu.dcache.total_refs 23580069 # Total number of references to valid blocks.
+system.cpu.dcache.total_refs 23580072 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 37.870747 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 37.870752 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 13150366 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13150366 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 9943631 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 9943631 # number of WriteReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data 13150368 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13150368 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 9943632 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 9943632 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 235999 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247136 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 23093997 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 23093997 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 23093997 # number of overall hits
-system.cpu.dcache.overall_hits::total 23093997 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 23094000 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 23094000 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 23094000 # number of overall hits
+system.cpu.dcache.overall_hits::total 23094000 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 364548 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 249897 # number of WriteReq misses
system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 614445 # number of overall misses
system.cpu.dcache.overall_misses::total 614445 # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data 13514914 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 13514914 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10193528 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10193528 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 13514916 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 13514916 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10193529 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10193529 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247137 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247136 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 23708442 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 23708442 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 23708442 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 23708442 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 23708445 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 23708445 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 23708445 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 23708445 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026974 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024515 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045068 # miss rate for LoadLockedReq accesses
header_cycles=1
use_default_range=false
width=64
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
max_mem_size=268435456
mem_start_addr=0
system=system
pio=system.iobus.master[1]
-[system.realview.rtc_fake]
-type=AmbaFake
-amba_id=266289
-ignore_access=false
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+gic=system.realview.gic
+int_delay=100000
+int_num=42
pio_addr=268529664
pio_latency=1000
system=system
+time=Thu Jan 1 00:00:00 2009
pio=system.iobus.master[23]
[system.realview.sci_fake]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 08:32:03
-gem5 started Mar 9 2012 08:33:32
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 16:36:56
gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
-The currently selected ARM platforms doesn't support
- the amount of DRAM you've selected. Please try
- another platform
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
sim_ticks 2669611225000 # Number of ticks simulated
final_tick 2669611225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 888599 # Simulator instruction rate (inst/s)
-host_op_rate 1136769 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38701401221 # Simulator tick rate (ticks/s)
-host_mem_usage 381720 # Number of bytes of host memory used
-host_seconds 68.98 # Real time elapsed on the host
-sim_insts 61295262 # Number of instructions simulated
-sim_ops 78413959 # Number of ops (including micro ops) simulated
+host_inst_rate 887100 # Simulator instruction rate (inst/s)
+host_op_rate 1134851 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 38636092154 # Simulator tick rate (ticks/s)
+host_mem_usage 379132 # Number of bytes of host memory used
+host_seconds 69.10 # Real time elapsed on the host
+sim_insts 61295282 # Number of instructions simulated
+sim_ops 78413979 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.bw_write 3818629 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 54138623 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 127749 # number of replacements
-system.l2c.tagsinuse 26172.513439 # Cycle average of tags in use
-system.l2c.total_refs 1540412 # Total number of references to valid blocks.
+system.l2c.tagsinuse 26172.513447 # Cycle average of tags in use
+system.l2c.total_refs 1540413 # Total number of references to valid blocks.
system.l2c.sampled_refs 157158 # Sample count of references to valid blocks.
-system.l2c.avg_refs 9.801677 # Average number of references to valid blocks.
+system.l2c.avg_refs 9.801684 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 15197.869059 # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks 15197.869082 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 8.069070 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.114155 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 2680.486069 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 3670.979885 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 2680.486070 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 3670.979881 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 0.091092 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.itb.walker 0.000002 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 2441.904066 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 2173.000042 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 2441.904061 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 2173.000034 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.231901 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000123 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.399361 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 4237 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 1502 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 371106 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 371107 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 191753 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 4185 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 1874 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 499097 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 157046 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1230800 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1230801 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 589400 # number of Writeback hits
system.l2c.Writeback_hits::total 589400 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 1143 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::total 101060 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 4237 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 1502 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 371106 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 371107 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 234259 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 4185 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 1874 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 499097 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 215600 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1331860 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1331861 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 4237 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 1502 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 371106 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 371107 # number of overall hits
system.l2c.overall_hits::cpu0.data 234259 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 4185 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 1874 # number of overall hits
system.l2c.overall_hits::cpu1.inst 499097 # number of overall hits
system.l2c.overall_hits::cpu1.data 215600 # number of overall hits
-system.l2c.overall_hits::total 1331860 # number of overall hits
+system.l2c.overall_hits::total 1331861 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 24 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 14 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 7728 # number of ReadReq misses
system.l2c.overall_miss_latency::total 9564047500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 4261 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 1516 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 378834 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 378835 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 202680 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 4193 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 1878 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 506630 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 165547 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1265539 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1265540 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 589400 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 589400 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 4658 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 249908 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 4261 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 1516 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 378834 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 378835 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 342510 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 4193 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 1878 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 506630 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 275625 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1515447 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1515448 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 4261 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 1516 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 378834 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 378835 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 342510 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 4193 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 1878 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 506630 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 275625 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1515447 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1515448 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.005632 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.009235 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.020399 # miss rate for ReadReq accesses
system.cpu0.num_int_alu_accesses 39881498 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 4107 # Number of float alu accesses
system.cpu0.num_func_calls 977479 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4566516 # number of instructions that are conditional controls
+system.cpu0.num_conditional_control_insts 4455595 # number of instructions that are conditional controls
system.cpu0.num_int_insts 39881498 # number of integer instructions
system.cpu0.num_fp_insts 4107 # number of float instructions
system.cpu0.num_int_register_reads 225043856 # number of times the integer registers were read
system.cpu0.num_mem_refs 14677999 # number of memory refs
system.cpu0.num_load_insts 8148547 # Number of load instructions
system.cpu0.num_store_insts 6529452 # Number of store instructions
-system.cpu0.num_idle_cycles 5107410781.564784 # Number of idle cycles
-system.cpu0.num_busy_cycles 230394434.435216 # Number of busy cycles
+system.cpu0.num_idle_cycles 5107410767.568501 # Number of idle cycles
+system.cpu0.num_busy_cycles 230394448.431500 # Number of busy cycles
system.cpu0.not_idle_fraction 0.043163 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.956837 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 38525 # number of quiesce instructions executed
-system.cpu0.icache.replacements 380069 # number of replacements
+system.cpu0.icache.replacements 380070 # number of replacements
system.cpu0.icache.tagsinuse 510.849663 # Cycle average of tags in use
-system.cpu0.icache.total_refs 35367311 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 380581 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 92.929786 # Average number of references to valid blocks.
+system.cpu0.icache.total_refs 35367310 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 380582 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 92.929539 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 74921716000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 510.849663 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.997753 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.997753 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 35367311 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 35367311 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 35367311 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 35367311 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 35367311 # number of overall hits
-system.cpu0.icache.overall_hits::total 35367311 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 380583 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 380583 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 380583 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 380583 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 380583 # number of overall misses
-system.cpu0.icache.overall_misses::total 380583 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5651439000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 5651439000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 5651439000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 5651439000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 5651439000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 5651439000 # number of overall miss cycles
+system.cpu0.icache.ReadReq_hits::cpu0.inst 35367310 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 35367310 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 35367310 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 35367310 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 35367310 # number of overall hits
+system.cpu0.icache.overall_hits::total 35367310 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 380584 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 380584 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 380584 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 380584 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 380584 # number of overall misses
+system.cpu0.icache.overall_misses::total 380584 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5651447000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 5651447000 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 5651447000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 5651447000 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 5651447000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 5651447000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 35747894 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 35747894 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 35747894 # number of demand (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010646 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010646 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010646 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14849.425749 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14849.425749 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14849.425749 # average overall miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14849.407752 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14849.407752 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14849.407752 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.writebacks::writebacks 12960 # number of writebacks
system.cpu0.icache.writebacks::total 12960 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 380583 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 380583 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 380583 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 380583 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 380583 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 380583 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4509188500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 4509188500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4509188500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 4509188500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4509188500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 4509188500 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 380584 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 380584 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 380584 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 380584 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 380584 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 380584 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4509193500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 4509193500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4509193500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 4509193500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4509193500 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 4509193500 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11848.090041 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11848.090041 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11848.090041 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 334596 # number of replacements
-system.cpu0.dcache.tagsinuse 450.118381 # Cycle average of tags in use
+system.cpu0.dcache.tagsinuse 450.118379 # Cycle average of tags in use
system.cpu0.dcache.total_refs 12875674 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 335004 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 38.434389 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 450.118381 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu0.data 450.118379 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.879137 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.879137 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 7428609 # number of ReadReq hits
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 7762496 # DTB read hits
+system.cpu1.dtb.read_hits 7762498 # DTB read hits
system.cpu1.dtb.read_misses 5432 # DTB read misses
-system.cpu1.dtb.write_hits 5411648 # DTB write hits
+system.cpu1.dtb.write_hits 5411649 # DTB write hits
system.cpu1.dtb.write_misses 1096 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.prefetch_faults 166 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 261 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 7767928 # DTB read accesses
-system.cpu1.dtb.write_accesses 5412744 # DTB write accesses
+system.cpu1.dtb.read_accesses 7767930 # DTB read accesses
+system.cpu1.dtb.write_accesses 5412745 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 13174144 # DTB hits
+system.cpu1.dtb.hits 13174147 # DTB hits
system.cpu1.dtb.misses 6528 # DTB misses
-system.cpu1.dtb.accesses 13180672 # DTB accesses
-system.cpu1.itb.inst_hits 26848280 # ITB inst hits
+system.cpu1.dtb.accesses 13180675 # DTB accesses
+system.cpu1.itb.inst_hits 26848300 # ITB inst hits
system.cpu1.itb.inst_misses 3154 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 26851434 # ITB inst accesses
-system.cpu1.itb.hits 26848280 # DTB hits
+system.cpu1.itb.inst_accesses 26851454 # ITB inst accesses
+system.cpu1.itb.hits 26848300 # DTB hits
system.cpu1.itb.misses 3154 # DTB misses
-system.cpu1.itb.accesses 26851434 # DTB accesses
+system.cpu1.itb.accesses 26851454 # DTB accesses
system.cpu1.numCycles 5339222450 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 25921760 # Number of instructions committed
-system.cpu1.committedOps 34444935 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 31033253 # Number of integer alu accesses
+system.cpu1.committedInsts 25921780 # Number of instructions committed
+system.cpu1.committedOps 34444955 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 31033271 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 5714 # Number of float alu accesses
system.cpu1.num_func_calls 1093852 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3529915 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 31033253 # number of integer instructions
+system.cpu1.num_conditional_control_insts 3472619 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 31033271 # number of integer instructions
system.cpu1.num_fp_insts 5714 # number of float instructions
-system.cpu1.num_int_register_reads 181157193 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 32585304 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 181157292 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 32585326 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 3770 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written
-system.cpu1.num_mem_refs 13796843 # number of memory refs
-system.cpu1.num_load_insts 8139019 # Number of load instructions
-system.cpu1.num_store_insts 5657824 # Number of store instructions
-system.cpu1.num_idle_cycles 4950307250.068146 # Number of idle cycles
-system.cpu1.num_busy_cycles 388915199.931854 # Number of busy cycles
+system.cpu1.num_mem_refs 13796846 # number of memory refs
+system.cpu1.num_load_insts 8139021 # Number of load instructions
+system.cpu1.num_store_insts 5657825 # Number of store instructions
+system.cpu1.num_idle_cycles 4950307196.068146 # Number of idle cycles
+system.cpu1.num_busy_cycles 388915253.931854 # Number of busy cycles
system.cpu1.not_idle_fraction 0.072841 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.927159 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 53838 # number of quiesce instructions executed
system.cpu1.icache.replacements 508221 # number of replacements
system.cpu1.icache.tagsinuse 497.375159 # Cycle average of tags in use
-system.cpu1.icache.total_refs 26339543 # Total number of references to valid blocks.
+system.cpu1.icache.total_refs 26339563 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 508733 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 51.774788 # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs 51.774827 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 191336880000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 497.375159 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.971436 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.971436 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 26339543 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 26339543 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 26339543 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 26339543 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 26339543 # number of overall hits
-system.cpu1.icache.overall_hits::total 26339543 # number of overall hits
+system.cpu1.icache.ReadReq_hits::cpu1.inst 26339563 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 26339563 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 26339563 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 26339563 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 26339563 # number of overall hits
+system.cpu1.icache.overall_hits::total 26339563 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 508733 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 508733 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 508733 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 508733 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 508733 # number of overall misses
system.cpu1.icache.overall_misses::total 508733 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7436442000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 7436442000 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 7436442000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 7436442000 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 7436442000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 7436442000 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 26848276 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 26848276 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 26848276 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 26848276 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 26848276 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 26848276 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7436443000 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 7436443000 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 7436443000 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 7436443000 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 7436443000 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 7436443000 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 26848296 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 26848296 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 26848296 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 26848296 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 26848296 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 26848296 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018948 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018948 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018948 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14617.573462 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14617.573462 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14617.573462 # average overall miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14617.575428 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14617.575428 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14617.575428 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.demand_mshr_misses::total 508733 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 508733 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 508733 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5908060000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 5908060000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5908060000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 5908060000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5908060000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 5908060000 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5908061000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 5908061000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5908061000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 5908061000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5908061000 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 5908061000 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11613.282409 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11613.282409 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11613.282409 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11613.284375 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11613.284375 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11613.284375 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 295754 # number of replacements
-system.cpu1.dcache.tagsinuse 467.166427 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 11737107 # Total number of references to valid blocks.
+system.cpu1.dcache.tagsinuse 467.166428 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 11737110 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 296266 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 39.616787 # Average number of references to valid blocks.
+system.cpu1.dcache.avg_refs 39.616797 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 75924171000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 467.166427 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_blocks::cpu1.data 467.166428 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.912434 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.912434 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 6345290 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 6345290 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 5152610 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 5152610 # number of WriteReq hits
+system.cpu1.dcache.ReadReq_hits::cpu1.data 6345292 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 6345292 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 5152611 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 5152611 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 104795 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 104795 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 106403 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 106403 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 11497900 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 11497900 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 11497900 # number of overall hits
-system.cpu1.dcache.overall_hits::total 11497900 # number of overall hits
+system.cpu1.dcache.demand_hits::cpu1.data 11497903 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 11497903 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 11497903 # number of overall hits
+system.cpu1.dcache.overall_hits::total 11497903 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 188245 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 188245 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 137493 # number of WriteReq misses
system.cpu1.dcache.demand_misses::total 325738 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 325738 # number of overall misses
system.cpu1.dcache.overall_misses::total 325738 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2729023500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 2729023500 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2729025500 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 2729025500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4123985000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 4123985000 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131721000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 131721000 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131720000 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 131720000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 82493000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 82493000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 6853008500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 6853008500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 6853008500 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 6853008500 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 6533535 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 6533535 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 5290103 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 5290103 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.demand_miss_latency::cpu1.data 6853010500 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 6853010500 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 6853010500 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 6853010500 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 6533537 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 6533537 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 5290104 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 5290104 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 116352 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 116352 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 116309 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 116309 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 11823638 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 11823638 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 11823638 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 11823638 # number of overall (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data 11823641 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 11823641 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 11823641 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 11823641 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.028812 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025991 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099328 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085170 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027550 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027550 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14497.189832 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14497.200457 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29994.145156 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11397.508004 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11397.421476 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8327.579245 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21038.406634 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21038.406634 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21038.412773 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21038.412773 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.demand_mshr_misses::total 325738 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 325738 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 325738 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2164153000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2164153000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2164155000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2164155000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3711466500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3711466500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97050000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97050000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97049000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97049000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52793000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52793000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5875619500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 5875619500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5875619500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 5875619500 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137931975000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137931975000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 470526000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 470526000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 138402501000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 138402501000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5875621500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 5875621500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5875621500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 5875621500 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137931976000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137931976000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 470527000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 470527000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 138402503000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 138402503000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028812 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025991 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099328 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085118 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11496.470026 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11496.480650 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26993.857869 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8397.508004 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8397.421476 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5332.626263 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.869392 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18037.869392 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.875532 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18037.875532 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
header_cycles=1
use_default_range=false
width=64
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
max_mem_size=268435456
mem_start_addr=0
system=system
pio=system.iobus.master[1]
-[system.realview.rtc_fake]
-type=AmbaFake
-amba_id=266289
-ignore_access=false
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+gic=system.realview.gic
+int_delay=100000
+int_num=42
pio_addr=268529664
pio_latency=1000
system=system
+time=Thu Jan 1 00:00:00 2009
pio=system.iobus.master[23]
[system.realview.sci_fake]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 08:32:03
-gem5 started Mar 9 2012 08:33:32
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 16:35:38
gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
-The currently selected ARM platforms doesn't support
- the amount of DRAM you've selected. Please try
- another platform
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
sim_ticks 2591441692000 # Number of ticks simulated
final_tick 2591441692000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 886915 # Simulator instruction rate (inst/s)
-host_op_rate 1133159 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38905818967 # Simulator tick rate (ticks/s)
-host_mem_usage 380156 # Number of bytes of host memory used
-host_seconds 66.61 # Real time elapsed on the host
-sim_insts 59075683 # Number of instructions simulated
-sim_ops 75477515 # Number of ops (including micro ops) simulated
+host_inst_rate 879685 # Simulator instruction rate (inst/s)
+host_op_rate 1123921 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 38588641896 # Simulator tick rate (ticks/s)
+host_mem_usage 377580 # Number of bytes of host memory used
+host_seconds 67.16 # Real time elapsed on the host
+sim_insts 59075703 # Number of instructions simulated
+sim_ops 75477535 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.bw_write 3717742 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 55293438 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 117809 # number of replacements
-system.l2c.tagsinuse 24928.376904 # Cycle average of tags in use
-system.l2c.total_refs 1535240 # Total number of references to valid blocks.
+system.l2c.tagsinuse 24929.234619 # Cycle average of tags in use
+system.l2c.total_refs 1535239 # Total number of references to valid blocks.
system.l2c.sampled_refs 146709 # Sample count of references to valid blocks.
-system.l2c.avg_refs 10.464525 # Average number of references to valid blocks.
+system.l2c.avg_refs 10.464518 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 14588.908220 # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks 14588.908290 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker 6.963925 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker 0.970411 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst 5158.445831 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data 5173.088517 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst 5159.303507 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data 5173.088486 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.222609 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker 0.000106 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst 0.078712 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst 0.078725 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data 0.078935 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.380377 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.380390 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker 8825 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker 3670 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst 837469 # number of ReadReq hits
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 14970647 # DTB read hits
+system.cpu.dtb.read_hits 14970649 # DTB read hits
system.cpu.dtb.read_misses 7343 # DTB read misses
-system.cpu.dtb.write_hits 11215605 # DTB write hits
+system.cpu.dtb.write_hits 11215606 # DTB write hits
system.cpu.dtb.write_misses 2208 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.prefetch_faults 183 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 14977990 # DTB read accesses
-system.cpu.dtb.write_accesses 11217813 # DTB write accesses
+system.cpu.dtb.read_accesses 14977992 # DTB read accesses
+system.cpu.dtb.write_accesses 11217814 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 26186252 # DTB hits
+system.cpu.dtb.hits 26186255 # DTB hits
system.cpu.dtb.misses 9551 # DTB misses
-system.cpu.dtb.accesses 26195803 # DTB accesses
-system.cpu.itb.inst_hits 60357722 # ITB inst hits
+system.cpu.dtb.accesses 26195806 # DTB accesses
+system.cpu.itb.inst_hits 60357742 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 60362193 # ITB inst accesses
-system.cpu.itb.hits 60357722 # DTB hits
+system.cpu.itb.inst_accesses 60362213 # ITB inst accesses
+system.cpu.itb.hits 60357742 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
-system.cpu.itb.accesses 60362193 # DTB accesses
+system.cpu.itb.accesses 60362213 # DTB accesses
system.cpu.numCycles 5182883384 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 59075683 # Number of instructions committed
-system.cpu.committedOps 75477515 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 68255270 # Number of integer alu accesses
+system.cpu.committedInsts 59075703 # Number of instructions committed
+system.cpu.committedOps 75477535 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 68255288 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
system.cpu.num_func_calls 1975579 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7801778 # number of instructions that are conditional controls
-system.cpu.num_int_insts 68255270 # number of integer instructions
+system.cpu.num_conditional_control_insts 7643992 # number of instructions that are conditional controls
+system.cpu.num_int_insts 68255288 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
-system.cpu.num_int_register_reads 390835391 # number of times the integer registers were read
-system.cpu.num_int_register_writes 72984158 # number of times the integer registers were written
+system.cpu.num_int_register_reads 390835490 # number of times the integer registers were read
+system.cpu.num_int_register_writes 72984180 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
-system.cpu.num_mem_refs 27351734 # number of memory refs
-system.cpu.num_load_insts 15632521 # Number of load instructions
-system.cpu.num_store_insts 11719213 # Number of store instructions
-system.cpu.num_idle_cycles 4574345772.482235 # Number of idle cycles
-system.cpu.num_busy_cycles 608537611.517765 # Number of busy cycles
+system.cpu.num_mem_refs 27351737 # number of memory refs
+system.cpu.num_load_insts 15632523 # Number of load instructions
+system.cpu.num_store_insts 11719214 # Number of store instructions
+system.cpu.num_idle_cycles 4574345726.482235 # Number of idle cycles
+system.cpu.num_busy_cycles 608537657.517765 # Number of busy cycles
system.cpu.not_idle_fraction 0.117413 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.882587 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 82953 # number of quiesce instructions executed
system.cpu.icache.replacements 852971 # number of replacements
system.cpu.icache.tagsinuse 510.943281 # Cycle average of tags in use
-system.cpu.icache.total_refs 59504239 # Total number of references to valid blocks.
+system.cpu.icache.total_refs 59504259 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 853483 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 69.719302 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 18512998000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.avg_refs 69.719325 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 18513021000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.943281 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.997936 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.997936 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 59504239 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 59504239 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 59504239 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 59504239 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 59504239 # number of overall hits
-system.cpu.icache.overall_hits::total 59504239 # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst 59504259 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 59504259 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 59504259 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 59504259 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 59504259 # number of overall hits
+system.cpu.icache.overall_hits::total 59504259 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 853483 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 853483 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 853483 # number of demand (read+write) misses
system.cpu.icache.demand_miss_latency::total 12547128000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12547128000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12547128000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 60357722 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 60357722 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 60357722 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 60357722 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 60357722 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 60357722 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst 60357742 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 60357742 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 60357742 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 60357742 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 60357742 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 60357742 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014140 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.014140 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.014140 # miss rate for overall accesses
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 626903 # number of replacements
system.cpu.dcache.tagsinuse 511.875592 # Cycle average of tags in use
-system.cpu.dcache.total_refs 23615096 # Total number of references to valid blocks.
+system.cpu.dcache.total_refs 23615099 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 627415 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 37.638718 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 37.638722 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.875592 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999757 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 13170367 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13170367 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 9958094 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 9958094 # number of WriteReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data 13170369 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13170369 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 9958095 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 9958095 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236142 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 236142 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247592 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247592 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 23128461 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 23128461 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 23128461 # number of overall hits
-system.cpu.dcache.overall_hits::total 23128461 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 23128464 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 23128464 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 23128464 # number of overall hits
+system.cpu.dcache.overall_hits::total 23128464 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 368563 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 368563 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 250302 # number of WriteReq misses
system.cpu.dcache.demand_miss_latency::total 15398067500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 15398067500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 15398067500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 13538930 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 13538930 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10208396 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10208396 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 13538932 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 13538932 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10208397 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10208397 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247593 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247593 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247592 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247592 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 23747326 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 23747326 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 23747326 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 23747326 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 23747329 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 23747329 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 23747329 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 23747329 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027222 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024519 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046249 # miss rate for LoadLockedReq accesses
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:17:15
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 16:33:35
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 10389500 because target called exit()
+Exiting @ tick 10303500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000010 # Number of seconds simulated
-sim_ticks 10389500 # Number of ticks simulated
-final_tick 10389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 10303500 # Number of ticks simulated
+final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 29724 # Simulator instruction rate (inst/s)
-host_op_rate 37079 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 67113828 # Simulator tick rate (ticks/s)
-host_mem_usage 225376 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
+host_inst_rate 46836 # Simulator instruction rate (inst/s)
+host_op_rate 58425 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 104878029 # Simulator tick rate (ticks/s)
+host_mem_usage 222544 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 4600 # Number of instructions simulated
sim_ops 5739 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 25600 # Number of bytes read from this memory
+system.physmem.bytes_read 25664 # Number of bytes read from this memory
system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 400 # Number of read requests responded to by this memory
+system.physmem.num_reads 401 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 2464026180 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 1700178064 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 2464026180 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s)
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 0 # DTB read hits
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.numCycles 20780 # number of cpu cycles simulated
+system.cpu.numCycles 20608 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2550 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1890 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1987 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 688 # Number of BTB hits
+system.cpu.BPredUnit.lookups 2552 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 1875 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 474 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 2008 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 693 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 244 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 6285 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 13028 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2550 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2849 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1782 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 1735 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 6263 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 13044 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2552 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 930 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2846 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1780 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 1715 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 2028 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 296 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 12124 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.372402 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.762919 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 12075 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.376812 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.767860 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 9275 76.50% 76.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 244 2.01% 78.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 198 1.63% 80.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 226 1.86% 82.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 226 1.86% 83.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 278 2.29% 86.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 125 1.03% 87.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 139 1.15% 88.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1413 11.65% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 9229 76.43% 76.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 246 2.04% 78.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 197 1.63% 80.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 227 1.88% 81.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 225 1.86% 83.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 278 2.30% 86.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 120 0.99% 87.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 130 1.08% 88.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1423 11.78% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 12124 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.122714 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.626949 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6488 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 1902 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2634 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 56 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1044 # Number of cycles decode is squashing
+system.cpu.fetch.rateDist::total 12075 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.123835 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.632958 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6461 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 1883 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2624 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1046 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 175 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 14514 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 580 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1044 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 6777 # Number of cycles rename is idle
+system.cpu.decode.BranchMispred 174 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 14512 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 583 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1046 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 6744 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1438 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2397 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 194 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 13625 # Number of instructions processed by rename
+system.cpu.rename.serializeStallCycles 1422 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2398 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 13646 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 154 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 13271 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 62674 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 61282 # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 13298 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 62745 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 61353 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 7587 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 48 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 646 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2866 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1785 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 12 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 11782 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 9138 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5710 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 16685 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 12124 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.753712 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.440468 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 7614 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 44 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 614 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2865 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 11802 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 9165 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5733 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 16704 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 12075 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.759006 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.446143 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 8489 70.02% 70.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1331 10.98% 81.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 789 6.51% 87.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 561 4.63% 92.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 477 3.93% 96.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 294 2.42% 98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 126 1.04% 99.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 44 0.36% 99.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 13 0.11% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 8430 69.81% 69.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1334 11.05% 80.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 801 6.63% 87.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 552 4.57% 92.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 480 3.98% 96.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 289 2.39% 98.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 130 1.08% 99.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 44 0.36% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 12124 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 12075 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5491 60.09% 60.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2383 26.08% 86.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1254 13.72% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5502 60.03% 60.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.14% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2395 26.13% 86.27% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1258 13.73% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 9138 # Type of FU issued
-system.cpu.iq.rate 0.439750 # Inst issue rate
+system.cpu.iq.FU_type_0::total 9165 # Type of FU issued
+system.cpu.iq.rate 0.444730 # Inst issue rate
system.cpu.iq.fu_busy_cnt 215 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.023528 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 30688 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 17549 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8140 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate 0.023459 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 30696 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 17588 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9360 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1665 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1664 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 847 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 865 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1044 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 1046 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11839 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2866 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1785 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispatchedInsts 11855 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 180 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2865 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 326 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8635 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 425 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8667 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2152 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 498 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1 # number of nop insts executed
-system.cpu.iew.exec_refs 3325 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1404 # Number of branches executed
-system.cpu.iew.exec_stores 1195 # Number of stores executed
-system.cpu.iew.exec_rate 0.415544 # Inst execution rate
-system.cpu.iew.wb_sent 8328 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8156 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3863 # num instructions producing a value
-system.cpu.iew.wb_consumers 7813 # num instructions consuming a value
+system.cpu.iew.exec_refs 3351 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1406 # Number of branches executed
+system.cpu.iew.exec_stores 1199 # Number of stores executed
+system.cpu.iew.exec_rate 0.420565 # Inst execution rate
+system.cpu.iew.wb_sent 8349 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8167 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3874 # num instructions producing a value
+system.cpu.iew.wb_consumers 7832 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.392493 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.494432 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.396302 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.494637 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions
system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 6099 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 6115 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 11081 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.517914 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.332416 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 378 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 11030 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.520308 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.336045 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 8736 78.84% 78.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1106 9.98% 88.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 431 3.89% 92.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 257 2.32% 95.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 182 1.64% 96.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 177 1.60% 98.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 55 0.50% 98.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 39 0.35% 99.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 98 0.88% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 8688 78.77% 78.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1103 10.00% 88.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 433 3.93% 92.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 253 2.29% 94.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 182 1.65% 96.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 178 1.61% 98.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 56 0.51% 98.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 39 0.35% 99.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 98 0.89% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 11081 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 11030 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4600 # Number of instructions committed
system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.function_calls 82 # Number of function calls committed.
system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 22664 # The number of ROB reads
-system.cpu.rob.rob_writes 24737 # The number of ROB writes
-system.cpu.timesIdled 179 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 8656 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 22629 # The number of ROB reads
+system.cpu.rob.rob_writes 24771 # The number of ROB writes
+system.cpu.timesIdled 177 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 8533 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4600 # Number of Instructions Simulated
system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 4600 # Number of Instructions Simulated
-system.cpu.cpi 4.517391 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 4.517391 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.221367 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.221367 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 39570 # number of integer regfile reads
-system.cpu.int_regfile_writes 8020 # number of integer regfile writes
+system.cpu.cpi 4.480000 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 4.480000 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.223214 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.223214 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 39716 # number of integer regfile reads
+system.cpu.int_regfile_writes 8038 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 16023 # number of misc regfile reads
+system.cpu.misc_regfile_reads 16043 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
system.cpu.icache.replacements 2 # number of replacements
-system.cpu.icache.tagsinuse 152.513802 # Cycle average of tags in use
-system.cpu.icache.total_refs 1663 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 151.737773 # Cycle average of tags in use
+system.cpu.icache.total_refs 1665 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 5.618243 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 5.625000 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 152.513802 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.074470 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.074470 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 1663 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1663 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1663 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1663 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1663 # number of overall hits
-system.cpu.icache.overall_hits::total 1663 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses
-system.cpu.icache.overall_misses::total 365 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 12618000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 12618000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 12618000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 12618000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 12618000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 12618000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 2028 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 2028 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 2028 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 2028 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 2028 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 2028 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179980 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.179980 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.179980 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34569.863014 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 151.737773 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.074091 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.074091 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1665 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1665 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1665 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1665 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1665 # number of overall hits
+system.cpu.icache.overall_hits::total 1665 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
+system.cpu.icache.overall_misses::total 366 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 12617500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 12617500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 12617500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 12617500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 12617500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9837000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 9837000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9837000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 9837000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9837000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 9837000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33233.108108 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 87.512831 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2409 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 16.167785 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 87.512831 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.021365 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.021365 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.021303 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.021303 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1796 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1796 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits
-system.cpu.dcache.overall_hits::total 2389 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits
+system.cpu.dcache.overall_hits::total 2405 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses
system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
system.cpu.dcache.overall_misses::total 474 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 5506000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 5506000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 5541500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 5541500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 16350000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 16350000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 16350000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 16350000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 16385500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 16385500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 16385500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1966 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1966 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087179 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.165561 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.165561 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32388.235294 # average ReadReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3156500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 3156500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3192000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4658000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 4658000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4658000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 4658000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054872 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29500 # average ReadReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 189.446862 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 142.892597 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 46.554265 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.001421 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.005781 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 46.638961 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001423 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits
-system.cpu.l2cache.overall_hits::total 41 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
+system.cpu.l2cache.overall_hits::total 40 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 362 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 128 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 404 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 129 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 128 # number of overall misses
-system.cpu.l2cache.overall_misses::total 404 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9478000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2963500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 12441500 # number of ReadReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.data 129 # number of overall misses
+system.cpu.l2cache.overall_misses::total 405 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9475500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2999000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 12474500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 9478000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 4410000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 13888000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 9478000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 4410000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 13888000 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 9475500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 4445500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 13921000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 9475500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 4445500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 13921000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.803738 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.859060 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.859060 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34340.579710 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34459.302326 # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2580000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11170500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11202500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3895000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 12485500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3895000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 12485500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.766355 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31463.414634 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:17:15
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 16:33:24
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 10389500 because target called exit()
+Exiting @ tick 10303500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000010 # Number of seconds simulated
-sim_ticks 10389500 # Number of ticks simulated
-final_tick 10389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 10303500 # Number of ticks simulated
+final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 31505 # Simulator instruction rate (inst/s)
-host_op_rate 39300 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 71135954 # Simulator tick rate (ticks/s)
-host_mem_usage 225060 # Number of bytes of host memory used
-host_seconds 0.15 # Real time elapsed on the host
+host_inst_rate 48410 # Simulator instruction rate (inst/s)
+host_op_rate 60388 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 108401694 # Simulator tick rate (ticks/s)
+host_mem_usage 222284 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 4600 # Number of instructions simulated
sim_ops 5739 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 25600 # Number of bytes read from this memory
+system.physmem.bytes_read 25664 # Number of bytes read from this memory
system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 400 # Number of read requests responded to by this memory
+system.physmem.num_reads 401 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 2464026180 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 1700178064 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 2464026180 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 20780 # number of cpu cycles simulated
+system.cpu.numCycles 20608 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2550 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1890 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1987 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 688 # Number of BTB hits
+system.cpu.BPredUnit.lookups 2552 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 1875 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 474 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 2008 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 693 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 244 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 6285 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 13028 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2550 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2849 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1782 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 1735 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 6263 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 13044 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2552 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 930 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2846 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1780 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 1715 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 2028 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 296 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 12124 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.372402 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.762919 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 12075 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.376812 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.767860 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 9275 76.50% 76.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 244 2.01% 78.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 198 1.63% 80.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 226 1.86% 82.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 226 1.86% 83.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 278 2.29% 86.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 125 1.03% 87.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 139 1.15% 88.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1413 11.65% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 9229 76.43% 76.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 246 2.04% 78.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 197 1.63% 80.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 227 1.88% 81.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 225 1.86% 83.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 278 2.30% 86.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 120 0.99% 87.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 130 1.08% 88.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1423 11.78% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 12124 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.122714 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.626949 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6488 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 1902 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2634 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 56 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1044 # Number of cycles decode is squashing
+system.cpu.fetch.rateDist::total 12075 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.123835 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.632958 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6461 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 1883 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2624 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1046 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 175 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 14514 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 580 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1044 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 6777 # Number of cycles rename is idle
+system.cpu.decode.BranchMispred 174 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 14512 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 583 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1046 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 6744 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1438 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2397 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 194 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 13625 # Number of instructions processed by rename
+system.cpu.rename.serializeStallCycles 1422 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2398 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 13646 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 154 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 13271 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 62674 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 61282 # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 13298 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 62745 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 61353 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 7587 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 48 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 646 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2866 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1785 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 12 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 11782 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 9138 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5710 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 16685 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 12124 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.753712 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.440468 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 7614 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 44 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 614 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2865 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 11802 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 9165 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5733 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 16704 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 12075 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.759006 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.446143 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 8489 70.02% 70.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1331 10.98% 81.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 789 6.51% 87.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 561 4.63% 92.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 477 3.93% 96.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 294 2.42% 98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 126 1.04% 99.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 44 0.36% 99.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 13 0.11% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 8430 69.81% 69.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1334 11.05% 80.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 801 6.63% 87.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 552 4.57% 92.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 480 3.98% 96.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 289 2.39% 98.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 130 1.08% 99.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 44 0.36% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 12124 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 12075 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5491 60.09% 60.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2383 26.08% 86.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1254 13.72% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5502 60.03% 60.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.14% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2395 26.13% 86.27% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1258 13.73% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 9138 # Type of FU issued
-system.cpu.iq.rate 0.439750 # Inst issue rate
+system.cpu.iq.FU_type_0::total 9165 # Type of FU issued
+system.cpu.iq.rate 0.444730 # Inst issue rate
system.cpu.iq.fu_busy_cnt 215 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.023528 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 30688 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 17549 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8140 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate 0.023459 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 30696 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 17588 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9360 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1665 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1664 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 847 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 865 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1044 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 1046 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11839 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2866 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1785 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispatchedInsts 11855 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 180 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2865 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 326 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8635 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 425 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8667 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2152 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 498 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1 # number of nop insts executed
-system.cpu.iew.exec_refs 3325 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1404 # Number of branches executed
-system.cpu.iew.exec_stores 1195 # Number of stores executed
-system.cpu.iew.exec_rate 0.415544 # Inst execution rate
-system.cpu.iew.wb_sent 8328 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8156 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3863 # num instructions producing a value
-system.cpu.iew.wb_consumers 7813 # num instructions consuming a value
+system.cpu.iew.exec_refs 3351 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1406 # Number of branches executed
+system.cpu.iew.exec_stores 1199 # Number of stores executed
+system.cpu.iew.exec_rate 0.420565 # Inst execution rate
+system.cpu.iew.wb_sent 8349 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8167 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3874 # num instructions producing a value
+system.cpu.iew.wb_consumers 7832 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.392493 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.494432 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.396302 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.494637 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions
system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 6099 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 6115 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 11081 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.517914 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.332416 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 378 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 11030 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.520308 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.336045 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 8736 78.84% 78.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1106 9.98% 88.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 431 3.89% 92.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 257 2.32% 95.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 182 1.64% 96.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 177 1.60% 98.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 55 0.50% 98.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 39 0.35% 99.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 98 0.88% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 8688 78.77% 78.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1103 10.00% 88.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 433 3.93% 92.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 253 2.29% 94.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 182 1.65% 96.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 178 1.61% 98.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 56 0.51% 98.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 39 0.35% 99.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 98 0.89% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 11081 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 11030 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4600 # Number of instructions committed
system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.function_calls 82 # Number of function calls committed.
system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 22664 # The number of ROB reads
-system.cpu.rob.rob_writes 24737 # The number of ROB writes
-system.cpu.timesIdled 179 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 8656 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 22629 # The number of ROB reads
+system.cpu.rob.rob_writes 24771 # The number of ROB writes
+system.cpu.timesIdled 177 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 8533 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4600 # Number of Instructions Simulated
system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 4600 # Number of Instructions Simulated
-system.cpu.cpi 4.517391 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 4.517391 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.221367 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.221367 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 39570 # number of integer regfile reads
-system.cpu.int_regfile_writes 8020 # number of integer regfile writes
+system.cpu.cpi 4.480000 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 4.480000 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.223214 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.223214 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 39716 # number of integer regfile reads
+system.cpu.int_regfile_writes 8038 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 16023 # number of misc regfile reads
+system.cpu.misc_regfile_reads 16043 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
system.cpu.icache.replacements 2 # number of replacements
-system.cpu.icache.tagsinuse 152.513802 # Cycle average of tags in use
-system.cpu.icache.total_refs 1663 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 151.737773 # Cycle average of tags in use
+system.cpu.icache.total_refs 1665 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 5.618243 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 5.625000 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 152.513802 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.074470 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.074470 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 1663 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1663 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1663 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1663 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1663 # number of overall hits
-system.cpu.icache.overall_hits::total 1663 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses
-system.cpu.icache.overall_misses::total 365 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 12618000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 12618000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 12618000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 12618000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 12618000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 12618000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 2028 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 2028 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 2028 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 2028 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 2028 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 2028 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179980 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.179980 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.179980 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34569.863014 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 151.737773 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.074091 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.074091 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1665 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1665 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1665 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1665 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1665 # number of overall hits
+system.cpu.icache.overall_hits::total 1665 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
+system.cpu.icache.overall_misses::total 366 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 12617500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 12617500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 12617500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 12617500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 12617500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9837000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 9837000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9837000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 9837000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9837000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 9837000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33233.108108 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 87.512831 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2409 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 16.167785 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 87.512831 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.021365 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.021365 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.021303 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.021303 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1796 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1796 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits
-system.cpu.dcache.overall_hits::total 2389 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits
+system.cpu.dcache.overall_hits::total 2405 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses
system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
system.cpu.dcache.overall_misses::total 474 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 5506000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 5506000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 5541500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 5541500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 16350000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 16350000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 16350000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 16350000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 16385500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 16385500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 16385500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1966 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1966 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087179 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.165561 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.165561 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32388.235294 # average ReadReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3156500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 3156500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3192000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4658000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 4658000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4658000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 4658000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054872 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29500 # average ReadReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 189.446862 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 142.892597 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 46.554265 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.001421 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.005781 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 46.638961 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001423 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits
-system.cpu.l2cache.overall_hits::total 41 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
+system.cpu.l2cache.overall_hits::total 40 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 362 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 128 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 404 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 129 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 128 # number of overall misses
-system.cpu.l2cache.overall_misses::total 404 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9478000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2963500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 12441500 # number of ReadReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.data 129 # number of overall misses
+system.cpu.l2cache.overall_misses::total 405 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9475500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2999000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 12474500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 9478000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 4410000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 13888000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 9478000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 4410000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 13888000 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 9475500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 4445500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 13921000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 9475500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 4445500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 13921000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.803738 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.859060 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.859060 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34340.579710 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34459.302326 # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2580000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11170500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11202500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3895000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 12485500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3895000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 12485500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.766355 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31463.414634 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:17:15
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 16:33:56
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 2875500 # Number of ticks simulated
final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 25080 # Simulator instruction rate (inst/s)
-host_op_rate 31285 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 15673750 # Simulator tick rate (ticks/s)
-host_mem_usage 214860 # Number of bytes of host memory used
-host_seconds 0.18 # Real time elapsed on the host
+host_inst_rate 95261 # Simulator instruction rate (inst/s)
+host_op_rate 118814 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 59514762 # Simulator tick rate (ticks/s)
+host_mem_usage 212272 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 4600 # Number of instructions simulated
sim_ops 5739 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 22944 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 185 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls
system.cpu.num_int_insts 4985 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 25237 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:17:15
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 16:33:45
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 2875500 # Number of ticks simulated
final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 24562 # Simulator instruction rate (inst/s)
-host_op_rate 30640 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 15350765 # Simulator tick rate (ticks/s)
-host_mem_usage 214764 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
+host_inst_rate 126142 # Simulator instruction rate (inst/s)
+host_op_rate 157316 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 78793699 # Simulator tick rate (ticks/s)
+host_mem_usage 212180 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
sim_insts 4600 # Number of instructions simulated
sim_ops 5739 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 22944 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 185 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls
system.cpu.num_int_insts 4985 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 25237 # number of times the integer registers were read
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 9 2012 10:15:20
-gem5 started Mar 9 2012 10:17:15
-gem5 executing on zizzer
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 16:34:06
+gem5 executing on u200540-lin
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 26361000 # Number of ticks simulated
final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 29458 # Simulator instruction rate (inst/s)
-host_op_rate 36586 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 169706423 # Simulator tick rate (ticks/s)
-host_mem_usage 223936 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
+host_inst_rate 140316 # Simulator instruction rate (inst/s)
+host_op_rate 174230 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 807994403 # Simulator tick rate (ticks/s)
+host_mem_usage 221092 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
sim_insts 4574 # Number of instructions simulated
sim_ops 5682 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 22400 # Number of bytes read from this memory
system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 185 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls
system.cpu.num_int_insts 4985 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 28701 # number of times the integer registers were read
projects / gem5.git / commitdiff