Added function to skip determine_cpu_caches(). We may have to update this in the
future: see note below.
arch/alpha/alpha_memory.cc:
dev/ide_ctrl.cc:
dev/tsunamireg.h:
Added ULL for 64bit ints
kern/linux/linux_system.cc:
Added a function to skip determine_cpu_caches, right now it is only used for
printing in proc, however in the future we may either want to implement the SC_CTL
IPR register or manually set alpha_l1i_cacheshape, alpha_l1d_cacheshape,
alpha_l2_cacheshape, alpha_l3_cacheshape to ((size << 10) | (linesize>>1)<<4 | way)
kern/linux/linux_system.hh:
added event to skip determine_cpu_caches()
--HG--
extra : convert_revision :
1065f2091bbe6832b730af490f5b4672c2afedce
// sign extend the physical address properly
if (req->paddr & PA_UNCACHED_BIT_39 ||
req->paddr & PA_UNCACHED_BIT_40)
- req->paddr |= 0xf0000000000;
+ req->paddr |= 0xf0000000000ULL;
else
- req->paddr &= 0xffffffffff;
+ req->paddr &= 0xffffffffffULL;
} else {
// not a physical address: need to look up pte
// sign extend the physical address properly
if (req->paddr & PA_UNCACHED_BIT_39 ||
req->paddr & PA_UNCACHED_BIT_40)
- req->paddr |= 0xf0000000000;
+ req->paddr |= 0xf0000000000ULL;
else
- req->paddr &= 0xffffffffff;
+ req->paddr &= 0xffffffffffULL;
} else {
if (write)
pioInterface->addAddrRange(pri_cmd_addr,
pri_cmd_addr + pri_cmd_size - 1);
- pri_cmd_addr = ((pri_cmd_addr | 0xf0000000000) & PA_IMPL_MASK);
+ pri_cmd_addr = ((pri_cmd_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
break;
case PCI0_BASE_ADDR1:
pioInterface->addAddrRange(pri_ctrl_addr,
pri_ctrl_addr + pri_ctrl_size - 1);
- pri_ctrl_addr = ((pri_ctrl_addr | 0xf0000000000) & PA_IMPL_MASK);
+ pri_ctrl_addr = ((pri_ctrl_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
break;
case PCI0_BASE_ADDR2:
pioInterface->addAddrRange(sec_cmd_addr,
sec_cmd_addr + sec_cmd_size - 1);
- sec_cmd_addr = ((sec_cmd_addr | 0xf0000000000) & PA_IMPL_MASK);
+ sec_cmd_addr = ((sec_cmd_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
break;
case PCI0_BASE_ADDR3:
pioInterface->addAddrRange(sec_ctrl_addr,
sec_ctrl_addr + sec_ctrl_size - 1);
- sec_ctrl_addr = ((sec_ctrl_addr | 0xf0000000000) & PA_IMPL_MASK);
+ sec_ctrl_addr = ((sec_ctrl_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
break;
case PCI0_BASE_ADDR4:
if (pioInterface)
pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
- bmi_addr = ((bmi_addr | 0xf0000000000) & PA_IMPL_MASK);
+ bmi_addr = ((bmi_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
break;
}
}
#ifndef __TSUNAMIREG_H__
#define __TSUNAMIREG_H__
-#define ALPHA_K0SEG_BASE 0xfffffc0000000000
+#define ALPHA_K0SEG_BASE 0xfffffc0000000000ULL
// CChip Registers
#define TSDEV_CC_CSR 0x00
#define RTC_CONTROL_REGISTERD 13 // control register D
#define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1
-#define PCHIP_PCI0_MEMORY 0x10000000000
-#define PCHIP_PCI0_IO 0x101FC000000
+#define PCHIP_PCI0_MEMORY 0x10000000000ULL
+#define PCHIP_PCI0_IO 0x101FC000000ULL
#define TSUNAMI_PCI0_MEMORY ALPHA_K0SEG_BASE + PCHIP_PCI0_MEMORY
#define TSUNAMI_PCI0_IO ALPHA_K0SEG_BASE + PCHIP_PCI0_IO
skipDelayLoopEvent = new LinuxSkipDelayLoopEvent(&pcEventQueue,
"calibrate_delay");
+ skipCacheProbeEvent = new LinuxSkipFuncEvent(&pcEventQueue, "determine_cpu_caches");
+
/* debugPrintfEvent = new DebugPrintfEvent(&pcEventQueue,
"debug_printf", false);
debugPrintfrEvent = new DebugPrintfEvent(&pcEventQueue,
if (kernelSymtab->findAddress("calibrate_delay", addr))
skipDelayLoopEvent->schedule(addr+8);
+ if (kernelSymtab->findAddress("determine_cpu_caches", addr))
+ skipCacheProbeEvent->schedule(addr+8);
+
#if TRACING_ON
if (kernelSymtab->findAddress("printk", addr))
printfEvent->schedule(addr);
LinuxBadAddrEvent *badaddrEvent;
LinuxSkipFuncEvent *skipPowerStateEvent;
LinuxSkipFuncEvent *skipScavengeBootEvent;
+ LinuxSkipFuncEvent *skipCacheProbeEvent;
LinuxSkipIdeDelay50msEvent *skipIdeDelay50msEvent;
LinuxSkipDelayLoopEvent *skipDelayLoopEvent;
LinuxPrintfEvent *printfEvent;