However when moving to 64-bit digits (desirable because the algorithm
is `O(N^2)`) this in turn means that the estimate has to be computed
from a *128* bit dividend and a 64-bit divisor. Such an operation
-simply does not exist in most Scalar 64-bit ISAs. For Power ISA
-it would be necessary to implement Packed SIMD instructions
-and infrastructure in order to utilise `vdivuq` which is a 128/128
+simply does not exist in most Scalar 64-bit ISAs. Although Power ISA
+comes close with `divdeu` placing the dividend in the upper half
+of a 128-bit computation the lower half is zeros. Again Power ISA
+has a Packed SIMD instruction `vdivuq` which is a 128/128
(quad) divide, not a 128/64. Some investigation into
soft-implementations of 128/128 or 128/64 divide show it to be typically
implemented bit-wise, with all that implies.