latest fighting with litex to get pad directions connected up

diff --git a/Makefile b/Makefile
index da4eeec9072a8f2013efad3257cbdf2e0f167def..a56d541363fd1f9cb1f678dbaa961b2e93b28205 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -25,6 +25,12 @@ ls180:
        cp build/ls180/gateware/mem_3.init .
        cp build/ls180/gateware/mem_4.init .
        cp libresoc/libresoc.v .
+       yosys -p 'read_verilog libresoc.v' \
+             -p 'read_verilog ls180.v' \
+          -p 'write_verilog ls180_cvt.v'
+       yosys -p 'read_verilog ls180.v' \
+             -p 'read_verilog SPBlock_512W64B8W.v' \
+          -p 'write_ilang ls180_cvt.il'
        yosys -p 'read_verilog libresoc.v' \
           -p 'write_ilang libresoc_cvt.il'
        yosys -p 'read_verilog ls180.v' \

diff --git a/libresoc/core.py b/libresoc/core.py
index e1de6c327bd9f59a81281f645df997a939b1dbd9..cc41a382c14319341bac6b8b9ad2a2cb5d05c430 100644 (file)
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -41,7 +41,7 @@ def make_wb_slave(prefix, obj, simple=False):
     return res
 
 def make_pad(res, dirn, name, suffix, cpup, iop):
-    cpud, iod = ('o', 'o') if dirn else ('i', 'i')
+    cpud, iod = ('i', 'o') if dirn else ('o', 'i')
     cname = '%s_%s__core__%s' % (cpud, name, suffix)
     pname = '%s_%s__pad__%s' % (iod, name, suffix)
     print ("make pad", name, dirn, cpud, iod, cname, pname, suffix, cpup, iop)
@@ -125,10 +125,15 @@ def make_jtag_ioconn(res, pin, cpupads, iopads):
             oe_idx = 0
             pfx = pin+"_"
         print ("gpio tri", fn, pin, iotype, pin_name, scan_idx, idx)
-        cpup, iop = get_field(cpu, pfx+"i")[idx], get_field(io, pfx+"i")[idx]
+        # i pads
+        cpup, iop = get_field(cpu, pfx+"i")[idx], \
+                    get_field(io, pfx+"i")[idx]
         make_pad(res, False, name, "i", cpup, iop)
-        cpup, iop = get_field(cpu, pfx+"o")[idx], get_field(io, pfx+"o")[idx]
+        # o pads
+        cpup, iop = get_field(cpu, pfx+"o")[idx], \
+                    get_field(io, pfx+"o")[idx]
         make_pad(res, True, name, "o", cpup, iop)
+        # oe pads
         cpup, iop = get_field(cpu, pfx+"oe")[oe_idx], \
                     get_field(io, pfx+"oe")[oe_idx]
         make_pad(res, True, name, "oe", cpup, iop)
@@ -297,8 +302,12 @@ class LibreSoC(CPU):
             self.cpupads = {}
             iopads = {}
             litexmap = {}
-            subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
-                      'pwm', 'sd0', 'sdr'}
+            subset = {'uart', 'mtwi', 'eint', 'mspi0',
+                            'sdr'}
+            subset.add('gpio')
+            #subset.add('pwm')
+            #subset.add('mspi1')
+            #subset.add('sd0')
             for periph in subset:
                 origperiph = periph
                 num = None
@@ -317,13 +326,13 @@ class LibreSoC(CPU):
                 elif periph == 'sd':
                     periph, num = 'sdcard', None
                 litexmap[origperiph] = (periph, num)
-                self.cpupads[origperiph] = platform.request(periph, num)
-                iopads[origperiph] = self.pad_cm.request(periph, num)
+                self.cpupads[origperiph] = self.pad_cm.request(periph, num)
+                iopads[origperiph] = platform.request(periph, num)
                 if periph == 'sdram':
                     # special-case sdram clock
-                    ck = platform.request("sdram_clock")
-                    self.cpupads['sdram_clock'] = ck
                     ck = self.pad_cm.request("sdram_clock")
+                    self.cpupads['sdram_clock'] = ck
+                    ck = platform.request("sdram_clock")
                     iopads['sdram_clock'] = ck
 
             pinset = get_pinspecs(subset=subset)

diff --git a/libresoc/ls180.py b/libresoc/ls180.py
index 42ddf7bd372ec366d1bb31515c0652954d5b5a4c..8aa40c18a34010ff4d4fae95c4b90913cfeff3cf 100644 (file)
--- a/libresoc/ls180.py
+++ b/libresoc/ls180.py
@@ -145,6 +145,9 @@ def io():
 
     # not connected - eurgh have to adjust this to match the total pincount.
     num_nc = 24
+    num_nc += 4 # mspi1 comments out, litex problems 25mar2021
+    #num_nc += 6 # sd0 comments out, litex problems 25mar2021
+    num_nc += 2 # pwm comments out, litex problems 25mar2021
     nc = ' '.join("NC%d" % i for i in range(num_nc))
     _io.append(("nc", 0, Pins(nc), IOStandard("LVCMOS33")))
 

diff --git a/ls180soc.py b/ls180soc.py
index 53fd75462a130b5a6d1885e165965e80760a938a..0ed93e6507ca6b02d4309a00d47c3bbd38c1fede 100755 (executable)
--- a/ls180soc.py
+++ b/ls180soc.py
@@ -497,25 +497,27 @@ class LibreSoCSim(SoCCore):
 
         # SPI Master
         print ("cpupadkeys", self.cpu.cpupads.keys())
-        sd_clk_freq = 8e6
-        pads = self.cpu.cpupads['mspi0']
-        spimaster = SPIMaster(pads, 8, self.sys_clk_freq, sd_clk_freq)
-        spimaster.add_clk_divider()
-        setattr(self.submodules, 'spimaster', spimaster)
-        self.add_csr('spimaster')
-
-        # SPI SDCard (1 wide)
-        spi_clk_freq = 400e3
-        pads = self.cpu.cpupads['mspi1']
-        spisdcard = SPIMaster(pads, 8, self.sys_clk_freq, spi_clk_freq)
-        spisdcard.add_clk_divider()
-        setattr(self.submodules, 'spisdcard', spisdcard)
-        self.add_csr('spisdcard')
+        if hasattr(self.cpu.cpupads, 'mspi0'):
+            sd_clk_freq = 8e6
+            pads = self.cpu.cpupads['mspi0']
+            spimaster = SPIMaster(pads, 8, self.sys_clk_freq, sd_clk_freq)
+            spimaster.add_clk_divider()
+            setattr(self.submodules, 'spimaster', spimaster)
+            self.add_csr('spimaster')
+
+        if hasattr(self.cpu.cpupads, 'mspi1'):
+            # SPI SDCard (1 wide)
+            spi_clk_freq = 400e3
+            pads = self.cpu.cpupads['mspi1']
+            spisdcard = SPIMaster(pads, 8, self.sys_clk_freq, spi_clk_freq)
+            spisdcard.add_clk_divider()
+            setattr(self.submodules, 'spisdcard', spisdcard)
+            self.add_csr('spisdcard')
 
         # EINTs - very simple, wire up top 3 bits to ls180 "eint" pins
         eintpads = self.cpu.cpupads['eint']
         print ("eintpads", eintpads)
-        self.comb += self.cpu.interrupt[12:16].eq(eintpads)
+        self.comb += self.cpu.interrupt[13:16].eq(eintpads)
 
         # JTAG
         jtagpads = platform.request("jtag")
@@ -535,11 +537,12 @@ class LibreSoCSim(SoCCore):
             self.sync += self.dummy[i].eq(self.nc[i] | self.cpu.interrupt[0])
 
         # PWM
-        pwmpads = self.cpu.cpupads['pwm']
-        for i in range(2):
-            name = "pwm%d" % i
-            setattr(self.submodules, name, PWM(pwmpads[i]))
-            self.add_csr(name)
+        if hasattr(self.cpu.cpupads, 'pwm'):
+            pwmpads = self.cpu.cpupads['pwm']
+            for i in range(2):
+                name = "pwm%d" % i
+                setattr(self.submodules, name, PWM(pwmpads[i]))
+                self.add_csr(name)
 
         # I2C Master
         i2c_core_pads = self.cpu.cpupads['mtwi']
@@ -548,35 +551,36 @@ class LibreSoCSim(SoCCore):
 
         # SDCard -----------------------------------------------------
 
-        # Emulator / Pads
-        sdcard_pads = self.cpu.cpupads['sd0']
-
-        # Core
-        self.submodules.sdphy  = SDPHY(sdcard_pads,
-                                       self.platform.device, self.clk_freq)
-        self.submodules.sdcore = SDCore(self.sdphy)
-        self.add_csr("sdphy")
-        self.add_csr("sdcore")
-
-        # Block2Mem DMA
-        bus = wishbone.Interface(data_width=self.bus.data_width,
-                                 adr_width=self.bus.address_width)
-        self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus,
-                                    endianness=self.cpu.endianness)
-        self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
-        dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
-        dma_bus.add_master("sdblock2mem", master=bus)
-        self.add_csr("sdblock2mem")
-
-        # Mem2Block DMA
-        bus = wishbone.Interface(data_width=self.bus.data_width,
-                                 adr_width=self.bus.address_width)
-        self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus,
-                                            endianness=self.cpu.endianness)
-        self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
-        dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
-        dma_bus.add_master("sdmem2block", master=bus)
-        self.add_csr("sdmem2block")
+        if hasattr(self.cpu.cpupads, 'sd0'):
+            # Emulator / Pads
+            sdcard_pads = self.cpu.cpupads['sd0']
+
+            # Core
+            self.submodules.sdphy  = SDPHY(sdcard_pads,
+                                           self.platform.device, self.clk_freq)
+            self.submodules.sdcore = SDCore(self.sdphy)
+            self.add_csr("sdphy")
+            self.add_csr("sdcore")
+
+            # Block2Mem DMA
+            bus = wishbone.Interface(data_width=self.bus.data_width,
+                                     adr_width=self.bus.address_width)
+            self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus,
+                                        endianness=self.cpu.endianness)
+            self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
+            dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
+            dma_bus.add_master("sdblock2mem", master=bus)
+            self.add_csr("sdblock2mem")
+
+            # Mem2Block DMA
+            bus = wishbone.Interface(data_width=self.bus.data_width,
+                                     adr_width=self.bus.address_width)
+            self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus,
+                                                endianness=self.cpu.endianness)
+            self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
+            dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
+            dma_bus.add_master("sdmem2block", master=bus)
+            self.add_csr("sdmem2block")
 
         # Debug ---------------------------------------------------------------
         if not debug: