(set_attr "btver2_decode" "direct, double")
(set_attr "mode" "<MODE>")])
+(define_insn "*bmi_bextr_<mode>_cczonly"
+ [(set (reg:CCZ FLAGS_REG)
+ (compare:CCZ
+ (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "r,m")
+ (match_operand:SWI48 2 "register_operand" "r,r")]
+ UNSPEC_BEXTR)
+ (const_int 0)))
+ (clobber (match_scratch:SWI48 0 "=r,r"))]
+ "TARGET_BMI"
+ "bextr\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "type" "bitmanip")
+ (set_attr "btver2_decode" "direct, double")
+ (set_attr "mode" "<MODE>")])
+
(define_insn "*bmi_blsi_<mode>"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(and:SWI48
(set_attr "mode" "<MODE>")])
(define_mode_attr k [(SI "k") (DI "q")])
+
(define_insn "*bmi2_bzhi_<mode>3_1"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(zero_extract:SWI48
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
+(define_insn "*bmi2_bzhi_<mode>3_1_cczonly"
+ [(set (reg:CCZ FLAGS_REG)
+ (compare:CCZ
+ (zero_extract:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "rm")
+ (umin:SWI48
+ (zero_extend:SWI48 (match_operand:QI 2 "register_operand" "r"))
+ (match_operand:SWI48 3 "const_int_operand" "n"))
+ (const_int 0))
+ (const_int 0)))
+ (clobber (match_scratch:SWI48 0 "=r"))]
+ "TARGET_BMI2 && INTVAL (operands[3]) == <MODE_SIZE> * BITS_PER_UNIT"
+ "bzhi\t{%<k>2, %1, %0|%0, %1, %<k>2}"
+ [(set_attr "type" "bitmanip")
+ (set_attr "prefix" "vex")
+ (set_attr "mode" "<MODE>")])
+
(define_insn "bmi2_pdep_<mode>3"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")