move VCC/VSS inward

diff --git a/180nm_Oct2020/ls180.mdwn b/180nm_Oct2020/ls180.mdwn
index 9340ee2b177f49c0f6147075f38b008b2962543b..e0759609fde5ff93ef594b72781cdd51a51dbd36 100644 (file)
--- a/180nm_Oct2020/ls180.mdwn
+++ b/180nm_Oct2020/ls180.mdwn
@@ -8,19 +8,19 @@ auto-generated by [[pinouts.py]]
 
 | Pin | Mux0        | Mux1        | Mux2        | Mux3        |
 | --- | ----------- | ----------- | ----------- | ----------- |
-|   0 | N VSSE_6    |             |
-|   1 | N VDDE_6    |             |
-|   2 | N VDDI_6    |             |
-|   3 | N VSSI_6    |             |
-|  23 | N SYS_RST   |             |
-|  24 | N SYS_PLLSELA0 |             |
-|  25 | N SYS_PLLSELA1 |             |
-|  26 | N SYS_PLLCLK |             |
-|  27 | N SYS_PLLTESTOUT |             |
-|  28 | N VSSI_7    |             |
-|  29 | N VDDI_7    |             |
-|  30 | N VSSI_7    |             |
-|  31 | N VDDI_7    |             |
+|   6 | N VSSE_6    |             |
+|   7 | N VDDE_6    |             |
+|   8 | N VDDI_6    |             |
+|   9 | N VSSI_6    |             |
+|  22 | N VSSI_7    |             |
+|  23 | N VDDI_7    |             |
+|  24 | N VSSI_7    |             |
+|  25 | N VDDI_7    |             |
+|  27 | N SYS_RST   |             |
+|  28 | N SYS_PLLSELA0 |             |
+|  29 | N SYS_PLLSELA1 |             |
+|  30 | N SYS_PLLCLK |             |
+|  31 | N SYS_PLLTESTOUT |             |
 
 ## Bank E (32 pins, width 2)
 
@@ -240,12 +240,12 @@ SDRAM
 
 System Control
 
-* SYS_PLLCLK : N26/0
-* SYS_PLLSELA0 : N24/0
-* SYS_PLLSELA1 : N25/0
-* SYS_PLLTESTOUT : N27/0
+* SYS_PLLCLK : N30/0
+* SYS_PLLSELA0 : N28/0
+* SYS_PLLSELA1 : N29/0
+* SYS_PLLTESTOUT : N31/0
 * SYS_PLLVCOUT : E4/0
-* SYS_RST   : N23/0
+* SYS_RST   : N27/0
 
 ## UART0
 
@@ -262,15 +262,15 @@ Power
 * VDDE_1    : S31/0
 * VDDE_2    : W0/0
 * VDDE_3    : W31/0
-* VDDE_6    : N1/0
+* VDDE_6    : N7/0
 * VDDI_0    : S2/0
 * VDDI_1    : S29/0
 * VDDI_2    : W2/0
 * VDDI_3    : W29/0
 * VDDI_4    : E1/0 E2/0
 * VDDI_5    : E29/0 E31/0
-* VDDI_6    : N2/0
-* VDDI_7    : N29/0 N31/0
+* VDDI_6    : N8/0
+* VDDI_7    : N23/0 N25/0
 
 ## VSS
 
@@ -280,15 +280,15 @@ GND
 * VSSE_1    : S30/0
 * VSSE_2    : W1/0
 * VSSE_3    : W30/0
-* VSSE_6    : N0/0
+* VSSE_6    : N6/0
 * VSSI_0    : S3/0
 * VSSI_1    : S28/0
 * VSSI_2    : W3/0
 * VSSI_3    : W28/0
 * VSSI_4    : E0/0 E3/0
 * VSSI_5    : E28/0 E30/0
-* VSSI_6    : N3/0
-* VSSI_7    : N28/0 N30/0
+* VSSI_6    : N9/0
+* VSSI_7    : N22/0 N24/0
 
 # Pinmap for Libre-SOC 180nm
 
@@ -339,17 +339,17 @@ GND
 
 ## VDD
 
-* VDDE_6 1 N1/0
-* VDDI_6 2 N2/0
-* VDDI_7 29 N29/0
+* VDDE_6 7 N7/0
+* VDDI_6 8 N8/0
+* VDDI_7 23 N23/0
 * VDDI_4 33 E1/0
 * VDDI_5 61 E29/0
 
 ## VSS
 
-* VSSE_6 0 N0/0
-* VSSI_6 3 N3/0
-* VSSI_7 28 N28/0
+* VSSE_6 6 N6/0
+* VSSI_6 9 N9/0
+* VSSI_7 22 N22/0
 * VSSI_4 32 E0/0
 * VSSI_5 60 E28/0
 
@@ -357,11 +357,11 @@ GND
 
 
 
-* SYS_RST 23 N23/0
-* SYS_PLLSELA0 24 N24/0
-* SYS_PLLSELA1 25 N25/0
-* SYS_PLLCLK 26 N26/0
-* SYS_PLLTESTOUT 27 N27/0
+* SYS_RST 27 N27/0
+* SYS_PLLSELA0 28 N28/0
+* SYS_PLLSELA1 29 N29/0
+* SYS_PLLCLK 30 N30/0
+* SYS_PLLTESTOUT 31 N31/0
 * SYS_PLLVCOUT 36 E4/0
 
 ## MTWI
@@ -427,8 +427,8 @@ I2C.
 
 | Pin | Mux0        | Mux1        | Mux2        | Mux3        |
 | --- | ----------- | ----------- | ----------- | ----------- |
-|  30 | N VSSI_7    |             |             |             |
-|  31 | N VDDI_7    |             |             |             |
+|  24 | N VSSI_7    |             |             |             |
+|  25 | N VDDI_7    |             |             |             |
 |  34 | E VDDI_4    |             |             |             |
 |  35 | E VSSI_4    |             |             |             |
 |  62 | E VSSI_5    |             |             |             |