(andsi3+6): Replace bad clrbit pattern with two working ones.

From-SVN: r7585

diff --git a/gcc/config/i960/i960.md b/gcc/config/i960/i960.md
index dd52829104309014545c37cd5ec6e4f164ff4d77..5a93cfe0455347ee617ac719554961cc419e61de 100644 (file)
--- a/gcc/config/i960/i960.md
+++ b/gcc/config/i960/i960.md
@@ -1657,14 +1657,25 @@
   return \"clrbit      %2,%1,%0\";
 }")
 
+;; (not (ashift 1 reg)) canonicalizes to (rotate -2 reg)
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d")
-       (and:SI (ashift:SI (const_int 1)
+       (and:SI (rotate:SI (const_int -2)
                           (match_operand:SI 1 "register_operand" "d"))
-               (match_operand:SI 2 "arith_operand" "dI")))]
+               (match_operand:SI 2 "register_operand" "d")))]
   ""
   "clrbit      %1,%2,%0")
 
+;; The above pattern canonicalizes to this when both the input and output
+;; are the same pseudo-register.
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "=d")
+                        (const_int 1)
+                        (match_operand:SI 1 "register_operand" "d"))
+       (const_int 0))]
+  ""
+  "clrbit      %1,%0,%0")
+
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d")
        (xor:SI (match_operand:SI 1 "arith_operand" "dI")