ARM: Squash the low order bits of the PC when performing a regular branch.

diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index 23c04306d5364cb4972b6e66ddcc39bdccf63e8c..c0d3136804cc36a99ee4f64d113211f528290c3b 100644 (file)
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -221,7 +221,13 @@ class ArmStaticInst : public StaticInst
     static void
     setNextPC(XC *xc, Addr val)
     {
-        xc->setNextPC((xc->readNextPC() & PcModeMask) |
+        Addr npc = xc->readNextPC();
+        if (npc & (ULL(1) << PcTBitShift)) {
+            val &= ~mask(1);
+        } else {
+            val &= ~mask(2);
+        }
+        xc->setNextPC((npc & PcModeMask) |
                       (val & ~PcModeMask));
     }
 

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 1a98a90873d86f77a1214bc06bd7263667318da4..a8b0b197a1af38fba5eafbf15edd0eb0ec0370a3 100644 (file)
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -70,10 +70,11 @@ let {{
     '''
     maybeAIWPCWrite = '''
         if (%(reg_idx)s == PCReg) {
-            if (xc->readPC() & (ULL(1) << PcTBitShift)) {
-                setIWNextPC(xc, %(final_val)s);
-            } else {
+            bool thumb = THUMB;
+            if (thumb) {
                 setNextPC(xc, %(final_val)s);
+            } else {
+                setIWNextPC(xc, %(final_val)s);
             }
         } else {
             xc->%(func)s(this, %(op_idx)s, %(final_val)s);