{"powerpc", PROCESSOR_POWERPC,
MASK_POWERPC | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
+ {"powerpc64", PROCESSOR_POWERPC64,
+ MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS,
+ POWER_MASKS | POWERPC_OPT_MASKS},
{"rios", PROCESSOR_RIOS1,
MASK_POWER | MASK_MULTIPLE | MASK_STRING,
MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
{"rios2", PROCESSOR_RIOS2,
MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2,
POWERPC_MASKS | MASK_NEW_MNEMONICS},
+ {"rs64a", PROCESSOR_RS64A,
+ MASK_POWERPC | MASK_NEW_MNEMONICS,
+ POWER_MASKS | POWERPC_OPT_MASKS},
{"401", PROCESSOR_PPC403,
MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"620", PROCESSOR_PPC620,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT},
+ {"630", PROCESSOR_PPC630,
+ MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+ POWER_MASKS | MASK_PPC_GPOPT},
{"740", PROCESSOR_PPC750,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
/* Identify the processor type */
rs6000_select[0].string = default_cpu;
- rs6000_cpu = PROCESSOR_DEFAULT;
+ rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
for (i = 0; i < sizeof (rs6000_select) / sizeof (rs6000_select[0]); i++)
{
}
/* Return 1 if the operand is a general register or memory operand without
- pre-inc or pre_dec which produces invalid form of PowerPC lwa
+ pre_inc or pre_dec which produces invalid form of PowerPC lwa
instruction. */
int
{
int regno;
+#if TARGET_ELF
/* We can not copy a symbolic operand directly into anything other than
BASE_REGS for TARGET_ELF. So indicate that a register from BASE_REGS
is needed as an intermediate register. */
- if (TARGET_ELF
- && class != BASE_REGS
+ if (class != BASE_REGS
&& (GET_CODE (in) == SYMBOL_REF
|| GET_CODE (in) == LABEL_REF
|| GET_CODE (in) == CONST))
return BASE_REGS;
+#endif
if (GET_CODE (in) == REG)
{
/* The second flow pass currently (June 1999) can't update regs_ever_live
without disturbing other parts of the compiler, so update it here to
make the prolog/epilogue code happy. */
- if (no_new_pseudos && !regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
+ if (no_new_pseudos && ! regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
current_function_uses_pic_offset_table = 1;
+
return pic_offset_table_rtx;
}
}
else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
fprintf (file, "%d(%s)", INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
- else if (TARGET_ELF && !TARGET_64BIT && GET_CODE (x) == LO_SUM
- && GET_CODE (XEXP (x, 0)) == REG && CONSTANT_P (XEXP (x, 1)))
+#if TARGET_ELF
+ else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
+ && CONSTANT_P (XEXP (x, 1)))
{
output_addr_const (file, XEXP (x, 1));
fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
}
+#endif
else
abort ();
}
else
{
if (TARGET_MINIMAL_TOC)
- fprintf (file, "\t.long %ld\n\t.long %ld\n",
+ fprintf (file, "\t.long 0x%lx\n\t.long 0x%lx\n",
(long)high, (long)low);
else
- fprintf (file, "\t.tc ID_%lx_%lx[TC],%ld,%ld\n",
+ fprintf (file, "\t.tc ID_%lx_%lx[TC],0x%lx,0x%lx\n",
(long)high, (long)low, (long)high, (long)low);
return;
}
case TYPE_IMUL:
case TYPE_IDIV:
- fprintf (stderr, "priority was %#x (%d) before adjustment\n", priority, priority);
+ fprintf (stderr, "priority was %#x (%d) before adjustment\n",
+ priority, priority);
if (priority >= 0 && priority < 0x01000000)
priority >>= 3;
break;
int get_issue_rate()
{
switch (rs6000_cpu_attr) {
- case CPU_RIOS1:
- return 3; /* ? */
- case CPU_RIOS2:
- return 4;
- case CPU_PPC601:
- return 3; /* ? */
+ case CPU_RIOS1: /* ? */
+ case CPU_RS64A:
+ case CPU_PPC601: /* ? */
+ return 3;
case CPU_PPC603:
- return 2;
case CPU_PPC750:
return 2;
+ case CPU_RIOS2:
case CPU_PPC604:
- return 4;
case CPU_PPC604E:
- return 4;
case CPU_PPC620:
+ case CPU_PPC630:
return 4;
default:
return 1;
if (is_attribute_p ("dllexport", identifier))
return (args == NULL_TREE);
- /* Exception attribute allows the user to specify 1-2 strings or identifiers
- that will fill in the 3rd and 4th fields of the structured exception
- table. */
+ /* Exception attribute allows the user to specify 1-2 strings
+ or identifiers that will fill in the 3rd and 4th fields
+ of the structured exception table. */
if (is_attribute_p ("exception", identifier))
{
int i;
rs6000_set_default_type_attributes (type)
tree type ATTRIBUTE_UNUSED;
{
+ return;
}
/* Return a dll import reference corresponding to a call's SYMBOL_REF */
strcat (p, call_name);
node = get_identifier (p);
- reg1 = force_reg (Pmode, gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)));
+ reg1 = force_reg (Pmode, gen_rtx_SYMBOL_REF (VOIDmode,
+ IDENTIFIER_POINTER (node)));
emit_move_insn (reg2, gen_rtx_MEM (Pmode, reg1));
return reg2;
}
-/* Return a reference suitable for calling a function with the longcall attribute. */
+/* Return a reference suitable for calling a function with the
+ longcall attribute. */
struct rtx_def *
rs6000_longcall_ref (call_ref)
rtx call_ref;
else if (TREE_CODE (decl) == VAR_DECL)
{
if ((flag_pic && reloc)
- || !TREE_READONLY (decl)
+ || ! TREE_READONLY (decl)
|| TREE_SIDE_EFFECTS (decl)
- || !DECL_INITIAL (decl)
+ || ! DECL_INITIAL (decl)
|| (DECL_INITIAL (decl) != error_mark_node
- && !TREE_CONSTANT (DECL_INITIAL (decl))))
+ && ! TREE_CONSTANT (DECL_INITIAL (decl))))
{
- if (rs6000_sdata != SDATA_NONE && (size > 0) && (size <= g_switch_value))
+ if (rs6000_sdata != SDATA_NONE && (size > 0)
+ && (size <= g_switch_value))
sdata_section ();
else
data_section ();
}
else
{
- if (rs6000_sdata != SDATA_NONE && (size > 0) && (size <= g_switch_value))
+ if (rs6000_sdata != SDATA_NONE && (size > 0)
+ && (size <= g_switch_value))
{
if (rs6000_sdata == SDATA_EABI)
sdata2_section ();
else
- sdata_section (); /* System V doesn't have .sdata2/.sbss2 */
+ sdata_section (); /* System V doesn't have .sdata2/.sbss2 */
}
else
const_section ();
}
\f
-
/* If we are referencing a function that is static or is known to be
in this file, make the SYMBOL_REF special. We can use this to indicate
that we can branch to this function without emitting a no-op after the
if ((size > 0 && size <= g_switch_value)
|| (name
- && ((len == sizeof (".sdata")-1 && strcmp (name, ".sdata") == 0)
- || (len == sizeof (".sdata2")-1 && strcmp (name, ".sdata2") == 0)
- || (len == sizeof (".sbss")-1 && strcmp (name, ".sbss") == 0)
- || (len == sizeof (".sbss2")-1 && strcmp (name, ".sbss2") == 0)
- || (len == sizeof (".PPC.EMB.sdata0")-1 && strcmp (name, ".PPC.EMB.sdata0") == 0)
- || (len == sizeof (".PPC.EMB.sbss0")-1 && strcmp (name, ".PPC.EMB.sbss0") == 0))))
+ && ((len == sizeof (".sdata")-1
+ && strcmp (name, ".sdata") == 0)
+ || (len == sizeof (".sdata2")-1
+ && strcmp (name, ".sdata2") == 0)
+ || (len == sizeof (".sbss")-1
+ && strcmp (name, ".sbss") == 0)
+ || (len == sizeof (".sbss2")-1
+ && strcmp (name, ".sbss2") == 0)
+ || (len == sizeof (".PPC.EMB.sdata0")-1
+ && strcmp (name, ".PPC.EMB.sdata0") == 0)
+ || (len == sizeof (".PPC.EMB.sbss0")-1
+ && strcmp (name, ".PPC.EMB.sbss0") == 0))))
{
rtx sym_ref = XEXP (DECL_RTL (decl), 0);
char *str = permalloc (2 + strlen (XSTR (sym_ref, 0)));
{
PROCESSOR_RIOS1,
PROCESSOR_RIOS2,
+ PROCESSOR_RS64A,
PROCESSOR_MPCCORE,
PROCESSOR_PPC403,
PROCESSOR_PPC601,
PROCESSOR_PPC604,
PROCESSOR_PPC604e,
PROCESSOR_PPC620,
+ PROCESSOR_PPC630,
PROCESSOR_PPC750
};
#define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
/* Define generic processor types based upon current deployment. */
-#define PROCESSOR_COMMON PROCESSOR_PPC601
-#define PROCESSOR_POWER PROCESSOR_RIOS1
-#define PROCESSOR_POWERPC PROCESSOR_PPC604
+#define PROCESSOR_COMMON PROCESSOR_PPC601
+#define PROCESSOR_POWER PROCESSOR_RIOS1
+#define PROCESSOR_POWERPC PROCESSOR_PPC604
+#define PROCESSOR_POWERPC64 PROCESSOR_RS64A
/* Define the default processor. This is overridden by other tm.h files. */
-#define PROCESSOR_DEFAULT PROCESSOR_RIOS1
+#define PROCESSOR_DEFAULT PROCESSOR_RIOS1
+#define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
/* Specify the dialect of assembler to use. New mnemonics is dialect one
and the old mnemonics are dialect zero. */
#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
if (GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
- (MODE) = (! TARGET_POWERPC64 ? SImode : DImode);
+ (MODE) = word_mode;
/* Define this if function arguments should also be promoted using the above
procedure. */
#define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \
(TARGET_ELF \
- && !flag_pic && !TARGET_TOC \
+ && ! flag_pic && ! TARGET_TOC \
&& (MODE) != DImode \
&& (MODE) != TImode \
&& (TARGET_HARD_FLOAT || (MODE) != DFmode) \
? COSTS_N_INSNS (5) \
: INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
+ case PROCESSOR_RS64A: \
+ return (GET_CODE (XEXP (X, 1)) != CONST_INT \
+ ? GET_MODE (XEXP (X, 1)) != DImode \
+ ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) \
+ : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
+ ? COSTS_N_INSNS (12) : COSTS_N_INSNS (14)); \
case PROCESSOR_RIOS2: \
case PROCESSOR_MPCCORE: \
case PROCESSOR_PPC604e: \
? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \
case PROCESSOR_PPC403: \
case PROCESSOR_PPC604: \
- case PROCESSOR_PPC620: \
return COSTS_N_INSNS (4); \
+ case PROCESSOR_PPC620: \
+ case PROCESSOR_PPC630: \
+ return (GET_CODE (XEXP (X, 1)) != CONST_INT \
+ ? GET_MODE (XEXP (X, 1)) != DImode \
+ ? COSTS_N_INSNS (4) : COSTS_N_INSNS (7) \
+ : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
+ ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
} \
case DIV: \
case MOD: \
return COSTS_N_INSNS (19); \
case PROCESSOR_RIOS2: \
return COSTS_N_INSNS (13); \
+ case PROCESSOR_RS64A: \
+ return (GET_MODE (XEXP (X, 1)) != DImode \
+ ? COSTS_N_INSNS (65) \
+ : COSTS_N_INSNS (67)); \
case PROCESSOR_MPCCORE: \
return COSTS_N_INSNS (6); \
case PROCESSOR_PPC403: \
return COSTS_N_INSNS (37); \
case PROCESSOR_PPC604: \
case PROCESSOR_PPC604e: \
- case PROCESSOR_PPC620: \
return COSTS_N_INSNS (20); \
+ case PROCESSOR_PPC620: \
+ case PROCESSOR_PPC630: \
+ return (GET_MODE (XEXP (X, 1)) != DImode \
+ ? COSTS_N_INSNS (21) \
+ : COSTS_N_INSNS (37)); \
case PROCESSOR_PPC750: \
return COSTS_N_INSNS (19); \
} \
\f
;; Define an insn type attribute. This is used in function unit delay
;; computations.
-(define_attr "type" "integer,load,store,fpload,fpstore,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
+(define_attr "type" "integer,load,store,fpload,fpstore,imul,lmul,idiv,ldiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
(const_string "integer"))
;; Length (in bytes).
;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in rs6000.h.
-(define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"
+(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"
(const (symbol_ref "rs6000_cpu_attr")))
; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
; (POWER and 601 use Integer Unit)
(define_function_unit "lsu" 1 0
(and (eq_attr "type" "load")
- (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620,ppc750"))
+ (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
2 1)
(define_function_unit "lsu" 1 0
(and (eq_attr "type" "store,fpstore")
- (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620,ppc750"))
+ (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
1 1)
(define_function_unit "lsu" 1 0
(define_function_unit "lsu" 1 0
(and (eq_attr "type" "fpload")
- (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
+ (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630"))
3 1)
(define_function_unit "iu" 1 0
(eq_attr "cpu" "rios2"))
1 1)
-; Integer Unit (RIOS1, PPC601, PPC603)
+; Integer Unit (RIOS1, PPC601, PPC603, RS64a)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "integer")
- (eq_attr "cpu" "rios1,mpccore,ppc403,ppc601,ppc603"))
+ (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc601,ppc603"))
1 1)
(define_function_unit "iu" 1 0
(eq_attr "cpu" "rios1,ppc601,ppc603"))
5 5)
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "imul")
+ (eq_attr "cpu" "rs64a"))
+ 20 14)
+
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "lmul")
+ (eq_attr "cpu" "rs64a"))
+ 34 34)
+
(define_function_unit "iu" 1 0
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "rios1"))
19 19)
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "idiv")
+ (eq_attr "cpu" "rs64a"))
+ 66 66)
+
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "ldiv")
+ (eq_attr "cpu" "rs64a"))
+ 66 66)
+
(define_function_unit "iu" 1 0
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "ppc403"))
; from/to spr).
(define_function_unit "iu2" 2 0
(and (eq_attr "type" "integer")
- (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
+ (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
1 1)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul")
- (eq_attr "cpu" "ppc604,ppc620"))
+ (eq_attr "cpu" "ppc604"))
4 2)
+(define_function_unit "imuldiv" 1 0
+ (and (eq_attr "type" "imul")
+ (eq_attr "cpu" "ppc620,ppc630"))
+ 5 3)
+
+(define_function_unit "imuldiv" 1 0
+ (and (eq_attr "type" "lmul")
+ (eq_attr "cpu" "ppc620,ppc630"))
+ 5 3)
+
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul")
(eq_attr "cpu" "ppc604e"))
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "idiv")
- (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
+ (eq_attr "cpu" "ppc604,ppc604e"))
20 19)
+(define_function_unit "imuldiv" 1 0
+ (and (eq_attr "type" "idiv")
+ (eq_attr "cpu" "ppc620"))
+ 37 36)
+
+(define_function_unit "imuldiv" 1 0
+ (and (eq_attr "type" "idiv")
+ (eq_attr "cpu" "ppc630"))
+ 21 20)
+
+(define_function_unit "imuldiv" 1 0
+ (and (eq_attr "type" "ldiv")
+ (eq_attr "cpu" "ppc620,ppc630"))
+ 37 36)
+
; PPC750 has two integer units: a primary one which can perform all
; operations and a secondary one which is fed in lock step with the first
; and can perform "simple" integer operations.
(define_function_unit "iu" 1 0
(and (eq_attr "type" "compare,delayed_compare")
- (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
+ (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
3 1)
(define_function_unit "iu2" 2 0
(define_function_unit "iu2" 2 0
(and (eq_attr "type" "compare,delayed_compare")
- (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc750"))
+ (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750"))
1 1)
; fp compare uses fp unit
; rios1 and rios2 have different fpcompare delays
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "fpcompare")
- (eq_attr "cpu" "rios2"))
+ (eq_attr "cpu" "rios2,ppc630"))
5 1)
; on ppc601 and ppc603, fpcompare takes also 2 cycles from
; fp compare uses fp unit
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "fpcompare")
- (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
+ (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
5 1)
(define_function_unit "fpu" 1 0
(define_function_unit "bpu" 1 0
(and (eq_attr "type" "mtjmpr")
- (eq_attr "cpu" "rios1,rios2"))
+ (eq_attr "cpu" "rios1,rios2,rs64a"))
5 1)
(define_function_unit "bpu" 1 0
(and (eq_attr "type" "mtjmpr")
- (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
+ (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
4 1)
; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "fp")
- (eq_attr "cpu" "mpccore"))
- 4 4)
+ (eq_attr "cpu" "rs64a,mpccore"))
+ 4 2)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "fp")
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "fp")
- (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750"))
+ (eq_attr "cpu" "ppc603,ppc750,ppc604,ppc604e,ppc620"))
3 1)
+(define_function_unit "fpu" 1 0
+ (and (eq_attr "type" "dmul")
+ (eq_attr "cpu" "rs64a"))
+ 7 2)
+
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "mpccore"))
(eq_attr "cpu" "rios1"))
19 19)
+(define_function_unit "fpu" 1 0
+ (and (eq_attr "type" "sdiv")
+ (eq_attr "cpu" "rs64a"))
+ 31 31)
+
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc601"))
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "ddiv")
- (eq_attr "cpu" "ppc601,ppc604,ppc604e,ppc620,ppc750"))
+ (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620"))
31 31)
(define_function_unit "fpu" 1 0
(eq_attr "cpu" "rios2"))
2 1)
+(define_function_unit "fpu2" 2 0
+ (and (eq_attr "type" "fp")
+ (eq_attr "cpu" "ppc630"))
+ 3 1)
+
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "rios2"))
2 1)
+(define_function_unit "fpu2" 2 0
+ (and (eq_attr "type" "dmul")
+ (eq_attr "cpu" "ppc630"))
+ 3 1)
+
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "sdiv,ddiv")
(eq_attr "cpu" "rios2"))
17 17)
+(define_function_unit "fpu2" 2 0
+ (and (eq_attr "type" "sdiv")
+ (eq_attr "cpu" "ppc630"))
+ 17 17)
+
+(define_function_unit "fpu2" 2 0
+ (and (eq_attr "type" "ddiv")
+ (eq_attr "cpu" "ppc630"))
+ 21 21)
+
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "ssqrt,dsqrt")
(eq_attr "cpu" "rios2"))
26 26)
+(define_function_unit "fpu2" 2 0
+ (and (eq_attr "type" "ssqrt")
+ (eq_attr "cpu" "ppc630"))
+ 18 18)
+
+(define_function_unit "fpu2" 2 0
+ (and (eq_attr "type" "dsqrt")
+ (eq_attr "cpu" "ppc630"))
+ 26 26)
+
\f
;; Start with fixed-point load and store insns. Here we put only the more
;; complex forms. Basic data transfer is done later.
(match_operand:DI 2 "gpc_reg_operand" "r")))]
"TARGET_POWERPC64"
"mulld %0,%1,%2"
- [(set_attr "type" "imul")])
+ [(set_attr "type" "lmul")])
(define_insn "smuldi3_highpart"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(const_int 64))))]
"TARGET_POWERPC64"
"mulhd %0,%1,%2"
- [(set_attr "type" "imul")])
+ [(set_attr "type" "lmul")])
(define_insn "umuldi3_highpart"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(const_int 64))))]
"TARGET_POWERPC64"
"mulhdu %0,%1,%2"
- [(set_attr "type" "imul")])
+ [(set_attr "type" "lmul")])
(define_expand "divdi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(match_operand:DI 2 "gpc_reg_operand" "r")))]
"TARGET_POWERPC64"
"divd %0,%1,%2"
- [(set_attr "type" "idiv")])
+ [(set_attr "type" "ldiv")])
(define_insn "udivdi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(match_operand:DI 2 "gpc_reg_operand" "r")))]
"TARGET_POWERPC64"
"divdu %0,%1,%2"
- [(set_attr "type" "idiv")])
+ [(set_attr "type" "ldiv")])
(define_insn "rotldi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
"sld%I2. %0,%1,%H2"
[(set_attr "type" "delayed_compare")])
+(define_insn ""
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "const_int_operand" "i"))
+ (match_operand:DI 3 "mask64_operand" "S")))]
+ "((GET_CODE (operands[3]) == CONST_INT
+ ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1"
+ "rldic %0,%1,%H2,%S3")
+
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC
+ (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "const_int_operand" "i"))
+ (match_operand:DI 3 "mask64_operand" "S"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 4 "=r"))]
+ "((GET_CODE (operands[3]) == CONST_INT
+ ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1"
+ "rldic. %0,%1,%H2,%S3"
+ [(set_attr "type" "delayed_compare")])
+
+(define_insn ""
+ [(set (match_operand:CC 4 "cc_reg_operand" "=x")
+ (compare:CC
+ (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "const_int_operand" "i"))
+ (match_operand:DI 3 "mask64_operand" "S"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
+ "((GET_CODE (operands[3]) == CONST_INT
+ ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1"
+ "rldic. %0,%1,%H2,%S3"
+ [(set_attr "type" "delayed_compare")])
+
(define_expand "lshrdi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
else
return \"mr %0,%1\;mr %L0,%L1\";
case 1:
- /* If the low-address word is used in the address, we must load it
- last. Otherwise, load it first. Note that we cannot have
- auto-increment in that case since the address register is known to be
- dead. */
+ /* If the low-address word is used in the address, we must load
+ it last. Otherwise, load it first. Note that we cannot have
+ auto-increment in that case since the address register is
+ known to be dead. */
if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
- operands [1], 0))
+ operands[1], 0))
return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
else
return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
auto-increment in that case since the address register is known to be
dead. */
if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
- operands [1], 0))
+ operands[1], 0))
return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
else
return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
auto-increment in that case since the address register is known to be
dead. */
if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
- operands [1], 0))
+ operands[1], 0))
return \"ld %L0,%L1\;ld %0,%1\";
else
return \"ld%U1 %0,%1\;ld %L0,%L1\";
}")
(define_expand "ctrsi"
- [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "")
- (const_int 1))
- (label_ref (match_operand 1 "" ""))
- (pc)))
+ [(parallel [(set (pc)
+ (if_then_else (ne (match_operand:SI 0 "register_operand" "")
+ (const_int 1))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))
(set (match_dup 0)
(plus:SI (match_dup 0)
(const_int -1)))
"")
(define_expand "ctrdi"
- [(parallel [(set (pc) (if_then_else (ne (match_operand:DI 0 "register_operand" "")
- (const_int 1))
- (label_ref (match_operand 1 "" ""))
- (pc)))
+ [(parallel [(set (pc)
+ (if_then_else (ne (match_operand:DI 0 "register_operand" "")
+ (const_int 1))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))
(set (match_dup 0)
(plus:DI (match_dup 0)
(const_int -1)))
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