```
FRS <- FPADD32(FRT, FRB)
- sub <- FPSUB32(FRT, FRB)
- FRT <- FPMUL32(FRA, sub)
+ FRT <- FPMULADD32(FRT, FRA, FRB, 1, -1)
```
The Floating-Point operand in register FRT is added to the floating-point
result then multiplied by FRA to create an intermediate result that is
stored in FRT.
-The subtraction and multiply are treated as if they were `fsub`
-followed by `fmul`, not `fmsub`. The creation of FRS and FRT are
-treated as parallel independent operations.
+The add into FRS is treated exactly as `fadd`. The creation
+of the result FRT is exact!y that of `fmsub`. The creation of FRS and FRT are
+treated as parallel independent operations which occur at the same time.
Note that if Rc=1 an Illegal Instruction is raised.
Rc=1 is `RESERVED`