rtlil: Add `Design::select()` for selecting whole modules.
authorAlberto Gonzalez <boqwxp@airmail.cc>
Wed, 17 Jun 2020 20:28:56 +0000 (20:28 +0000)
committerAlberto Gonzalez <boqwxp@airmail.cc>
Fri, 19 Jun 2020 18:16:33 +0000 (18:16 +0000)
kernel/rtlil.h

index f3dc3af68ed33613b0099b314006c598e36dc31c..354823e3ba04b69dd12d16692dfd45ed67219f76 100644 (file)
@@ -1061,6 +1061,13 @@ struct RTLIL::Design
                return selected_member(module->name, member->name);
        }
 
+       template<typename T1> void select(T1 *module) {
+               if (selection_stack.size() > 0) {
+                       RTLIL::Selection &sel = selection_stack.back();
+                       sel.select(module);
+               }
+       }
+
        template<typename T1, typename T2> void select(T1 *module, T2 *member) {
                if (selection_stack.size() > 0) {
                        RTLIL::Selection &sel = selection_stack.back();