X86: Obey the PCD (cache disable) bit in the page tables.

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 4c8d96f8b1dae6ab1f0564c567b6f713dc4b0f1f..52d9cdf9cd9c5f6c9c99ea6a0236101ce3a6cae0 100644 (file)
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -653,6 +653,8 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
             Addr paddr = entry->paddr | (vaddr & (entry->size-1));
             DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
             req->setPaddr(paddr);
+            if (entry->uncacheable)
+                req->setFlags(Request::UNCACHEABLE);
         } else {
             //Use the address which already has segmentation applied.
             DPRINTF(TLB, "Paging disabled.\n");