move mtmsr and mtspr to trap and spr pipelines

diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv
index 20f4e78d72ec03cc448d8e9b091446cc0bebcc62..054d58ae02b5053c2c9f5d4d22bee0e9a9df3ae0 100644 (file)
--- a/openpower/isatables/minor_31.csv
+++ b/openpower/isatables/minor_31.csv
@@ -105,15 +105,15 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b1000000000,,,,,,,,,,,,,,,,,,,,,,,mcrxr,X
 0b1001000000,,,,,,,,,,,,,,,,,,,,,,,mcrxrx,X
 0b0000010011,CR,OP_MFCR,NONE,NONE,NONE,RT,WHOLE_REG,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mfcr/mfocrf,XFX
-0b0001010011,ALU,OP_MFMSR,NONE,NONE,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,mfmsr,X
-0b0101010011,ALU,OP_MFSPR,SPR,NONE,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mfspr,XFX
+0b0001010011,TRAP,OP_MFMSR,NONE,NONE,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,mfmsr,X
+0b0101010011,SPR,OP_MFSPR,SPR,NONE,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mfspr,XFX
 0b0100001001,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,modud,X
 0b0100001011,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,moduw,X
 0b1100001001,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,1,NONE,0,0,modsd,X
 0b1100001011,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,1,NONE,0,0,modsw,X
 0b0010010000,CR,OP_MTCRF,RS,NONE,NONE,NONE,WHOLE_REG,WHOLE_REG,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mtcrf/mtocrf,XFX
-0b0010110010,ALU,OP_MTMSRD,RS,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,mtmsrd # ignore top bits and d,X
-0b0111010011,ALU,OP_MTSPR,RS,NONE,NONE,SPR,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mtspr,XFX
+0b0010110010,TRAP,OP_MTMSRD,RS,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,mtmsrd # ignore top bits and d,X
+0b0111010011,SPR,OP_MTSPR,RS,NONE,NONE,SPR,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mtspr,XFX
 0b0001001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,mulhd,XO
 0b0000001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,mulhdu,XO
 0b0001001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,mulhw,XO