comb assignment now working

diff --git a/absyn.py b/absyn.py
index 12f1c0a2a46265994e874508337dfded4671d882..d52250206719fbefcd53b2dba3c660b529f8ef9a 100644 (file)
--- a/absyn.py
+++ b/absyn.py
@@ -10,13 +10,40 @@ from nmigen import Signal, Module, Const, Cat, Elaboratable
 
 """
 
+def port_decl_do_not_use(comment, dt, name):
+    if dt is None or dt.dims is None:
+        width = '' # width: 1
+    else:
+        width = dt.dims
+        # XXX TODO, better checking, should be using data structure... *sigh*
+        width = width[1:-1] # strip brackets
+        width = width.split(':')
+        assert width[0] == '0'
+        width = width[1]
+    return 'self.%s = Signal(%s) # %s' % (name, width, comment)
+
 indent_debug = 0
 
+class PortDecl:
+    def __init__(self,comment,dt,name):
+        self.comment = comment
+        self.dt=dt
+        self.name=name
+    def initNode(self):
+        return port_decl_do_not_use(self.comment,self.dt,self.name)
+
+class Assignment:
+    def __init__(self,left,op,right):
+        self.left = left
+        self.op = op
+        self.right = right
+
 class Absyn:
     def __init__(self):
         self.outputfile = open("output.py","w")
         self.outputfile.write(preamble)
         self.assign = []
+        self.ports = []
     def printpy(self,p):
         self.outputfile.write(str(p)+"\n")
     def assign(self,p):
@@ -36,28 +63,9 @@ class Absyn:
         return Leaf(token.NEWLINE, '\n')
         
     def port_decl(self,comment, dt, name):
-        return None # TODO
-
-    def initPorts(self,params,ports):
-        pass_stmt = Node(syms.pass_stmt ,[Leaf(token.NAME, "def __init__(self):#FIXME")])
-        if params:
-            params = [Leaf(token.LPAR, '(')] + params + [Leaf(token.RPAR, ')')]
-            fn = [Leaf(token.NAME, 'def'),
-                  Leaf(token.NAME, '__initXXX__', prefix=' '),
-                  Node(syms.parameters, params),
-                  Leaf(token.COLON, ':')]
-            fndef = Node(syms.funcdef, fn)
-            stmts = Node(syms.stmt, [fndef])
-        else:
-            stmts = Node(syms.small_stmt, [pass_stmt, Leaf(token.NEWLINE, '\n')])
-            stmts = Node(syms.stmt, [stmts])
-        
-        for port in ports:
-            stmts.children.append(self.indent(2))
-            stmts.children.append(port)
-            stmts.children.append(self.nl())
-
-        return stmts
+        port = PortDecl(comment,dt,name)
+        self.ports += [port]
+        return port
 
     def initFunc(self,ports,params):
         params = [Leaf(token.LPAR, '('),Leaf(token.NAME,"self")] + [Leaf(token.RPAR, ')')]
@@ -72,7 +80,7 @@ class Absyn:
         stmts = Node(syms.stmt, [fndef])
         for port in ports:
             stmts.children.append(self.indent(2))
-            stmts.children.append(port)
+            stmts.children.append(port.initNode())
             stmts.children.append(self.nl())
         return stmts
 
@@ -89,11 +97,23 @@ class Absyn:
         stmts.children.append(self.indent(2))
         stmts.children.append(Leaf(token.STRING,"m = Module()"))
         stmts.children.append(self.nl())
-        ##
+        
+
         for a in self.assign:
             stmts.children.append(self.indent(2))
-            stmts.children.append(Leaf(token.STRING,"#FIXME_ASSIGN"+str(list(a[8]))))
+            # m.d.sync += self.left.eq(right)
+            stmts.children.append(Leaf(token.STRING,"m.d.comb += self."))
+            stmts.children.append(Leaf(token.STRING,a.left))
+            stmts.children.append(Leaf(token.STRING,".eq(self."))
+            stmts.children.append(Leaf(token.STRING,a.right))
+            stmts.children.append(Leaf(token.STRING,")"))
             stmts.children.append(self.nl())
+        
+        #for a in self.assign:
+        #    
+            #
+            #ports = a[8]
+        #    
             
         stmts.children.append(self.indent(2))                      
         stmts.children.append(Leaf(token.STRING,"return m"))                      
@@ -123,9 +143,11 @@ class Absyn:
         clsdecl = Node(syms.compound_stmt, [clsdecl])
         
         self.printpy(str(clsdecl))
+        print("=====================")
+        print(str(clsdecl))
         return clsdecl
 
     # combinatorical assign
     def cont_assign_1(self,p):
-       #self.printpy("#ASSIGN"+str(list(p)))
-       self.assign += [p]
+       print("#ASSIGN:BROKEN"+str(list(p)))
+       self.assign += [Assignment(p[1],p[2],p[3])]

diff --git a/examples/assignment.sv b/examples/assignment.sv
index e3e326e6dc5fd34f80a694225da883c5b2643b54..81831a2cd54fe75751cbd095ef6653471a3ba388 100644 (file)
--- a/examples/assignment.sv
+++ b/examples/assignment.sv
@@ -1,6 +1,6 @@
 module assignment(
-    input i, 
-    output o
+    output o,
+    input i
 );
 assign o = i;
 endmodule

diff --git a/parse_sv.py b/parse_sv.py
index bd760f5e506ebaa059ad1d679ee147ba63906e2d..fd25dbfc83c7179ed73af7909499cce11a80690b 100644 (file)
--- a/parse_sv.py
+++ b/parse_sv.py
@@ -109,18 +109,6 @@ class DataType:
         self.typ = typ
         self.signed = signed
 
-def port_decl_do_not_use(comment, dt, name):
-    if dt is None or dt.dims is None:
-        width = '' # width: 1
-    else:
-        width = dt.dims
-        # XXX TODO, better checking, should be using data structure... *sigh*
-        width = width[1:-1] # strip brackets
-        width = width.split(':')
-        assert width[0] == '0'
-        width = width[1]
-    return 'self.%s = Signal(%s) # %s' % (name, width, comment)
-
 # -------------- RULES ----------------
 ()
 def p_source_text_1(p):