+2014-11-21 Terry Guo <terry.guo@arm.com>
+
+ * config/tc-arm.c (md_assemble): Do not consider relaxation.
+ (md_convert_frag): Test and set target arch attribute accordingly.
+ (aeabi_set_attribute_string): Turn it into a global function.
+ * config/tc-arm.h (md_post_relax_hook): Enable it for ARM target.
+ (aeabi_set_public_attributes): Declare it.
+
2014-11-21 Terry Guo <terry.guo@arm.com>
* config/tc-arm.c (fpu_vfp_ext_armv8xd): New.
/* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
set those bits when Thumb-2 32-bit instructions are seen. ie.
anything other than bl/blx and v6-M instructions.
- This is overly pessimistic for relaxable instructions. */
- if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
- || inst.relax)
+ The impact of relaxable instructions will be considered later after we
+ finish all relaxation. */
+ if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
&& !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
fragp->fr_fix += fragp->fr_var;
+
+ /* Set whether we use thumb-2 ISA based on final relaxation results. */
+ if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
+ && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
+ ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
}
/* Return the size of a relaxable immediate operand instruction.
}
/* Set the public EABI object attributes. */
-static void
+void
aeabi_set_public_attributes (void)
{
int arch;
#define md_end arm_md_end
extern void arm_md_end (void);
bfd_boolean arm_is_eabi (void);
+
+#define md_post_relax_hook aeabi_set_public_attributes ()
+extern void aeabi_set_public_attributes (void);
#endif
/* NOTE: The fake label creation in stabs.c:s_stab_generic() has
+2014-11-21 Terry Guo <terry.guo@arm.com>
+
+ * gas/arm/attr-arch-assumption.d: New file.
+ * gas/arm/attr-arch-assumption.s: Likewise.
+
2014-11-21 Terry Guo <terry.guo@arm.com>
* gas/arm/armv7e-m+fpv5-d16.s: New.
--- /dev/null
+# name: arch and isa entries in elf attribute section
+# source: attr-arch-assumption.s
+# as:
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_arch: v4T
+ Tag_THUMB_ISA_use: Thumb-1
--- /dev/null
+ .syntax unified
+ .thumb
+foo:
+ cmp r0, r1
+ beq foo
+2014-11-21 Terry Guo <terry.guo@arm.com>
+
+ * ld-arm/tls-longplt-lib.s: Require ARMv6T2.
+ * ld-arm/tls-longplt.s: Likewise.
+ * ld-arm/tls-longplt-lib.d: Updated.
+ * ld-arm/tls-longplt.d: Likewise.
+
2014-11-21 Terry Guo <terry.guo@arm.com>
* ld-arm/attr-merge-vfp-4-sp.s: New test source file.
81e4: 000080b4 .word 0x000080b4
81e8: 4801 ldr r0, \[pc, #4\] ; .*
81ea: f7ff efe0 blx 81ac <.*>
- 81ee: 46c0 nop ; .*
+ 81ee: bf00 nop
81f0: 000080a5 .word 0x000080a5
Disassembly of section .foo:
400101c: fc00f284 .word 0xfc00f284
4001020: 4801 ldr r0, \[pc, #4\] ; .*
4001022: f000 e806 blx 4001030 .*
- 4001026: 46c0 nop ; .*
+ 4001026: bf00 nop
4001028: fc00f26d .word 0xfc00f26d
400102c: 00000000 .word 0x00000000
.syntax unified
+ .arch armv6t2
.text
text:
.arm
81e8: 000080d4 .word 0x000080d4
81ec: 4801 ldr r0, \[pc, #4\] ; .*
81ee: f7ff efe0 blx 81b0 .*
- 81f2: 46c0 nop ; .*
+ 81f2: bf00 nop
81f4: 000080c5 .word 0x000080c5
Disassembly of section .foo:
400101c: fc00f2a0 .word 0xfc00f2a0
4001020: 4801 ldr r0, \[pc, #4\] ; .*
4001022: f000 f809 bl 4001038 .*
- 4001026: 46c0 nop ; .*
+ 4001026: bf00 nop
4001028: fc00f291 .word 0xfc00f291
400102c: 00000000 .word 0x00000000
.syntax unified
+ .arch armv6t2
.text
text:
.arm