OpenPOWER CPU with
[[openpower/sv/bitmanip]] extensions
* 180/130 nm (TBD)
-* 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs
+* 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs with
+ [SRAM](https://github.com/adamgreig/daqnet/blob/master/gateware/daqnet/ethernet/rmii.py)
+ on-chip, built-in.
* 2x USB [[shakti/m_class/ULPI]] PHYs
* Direct DMA interface (independent bulk transfer)
* [JTAG](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD),