Merge pull request #513 from udif/pr_reg_wire_error

Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)

diff --cc frontends/ast/ast.cc
Simple merge

diff --cc frontends/ast/ast.h
Simple merge

diff --cc frontends/ast/simplify.cc
Simple merge

diff --cc frontends/verilog/verilog_lexer.l
Simple merge

diff --cc frontends/verilog/verilog_parser.y
Simple merge