Cleanup top modules and not used defines

diff --git a/tests/anlogic/fsm.v b/tests/anlogic/fsm.v
index 0605bd102ddd727902c9714bfe768abd4ab83f5b..368fbaace5e8a1e87b98b937646cc700f049c241 100644 (file)
--- a/tests/anlogic/fsm.v
+++ b/tests/anlogic/fsm.v
@@ -52,22 +52,4 @@
  endcase\r
  end\r
 \r
- endmodule\r
-\r
- module top (\r
-input clk,\r
-input rst,\r
-input a,\r
-input b,\r
-output g0,\r
-output g1\r
-);\r
-\r
-fsm u_fsm ( .clock(clk),\r
-            .reset(rst),\r
-            .req_0(a),\r
-            .req_1(b),\r
-            .gnt_0(g0),\r
-            .gnt_1(g1));\r
-\r
 endmodule\r

diff --git a/tests/anlogic/fsm.ys b/tests/anlogic/fsm.ys
index 6eb7b9a7139142caf8358e309bb5994ac5ccec86..76a5d3e432823c4706967d4de63ffa0f351f287e 100644 (file)
--- a/tests/anlogic/fsm.ys
+++ b/tests/anlogic/fsm.ys
@@ -1,12 +1,12 @@
 read_verilog fsm.v
-hierarchy -top top
+hierarchy -top fsm
 proc
-flatten
+#flatten
 #ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
 #equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
 equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd fsm # Constrain all select calls below inside the top module
 select -assert-count 1 t:AL_MAP_LUT2
 select -assert-count 5 t:AL_MAP_LUT5
 select -assert-count 1 t:AL_MAP_LUT6

diff --git a/tests/anlogic/shifter.v b/tests/anlogic/shifter.v
index c55632552a4c36f647143cf7ef51cbeec87acf94..04ae49d831f89b11863e1a6cde708b0b6d8a638e 100644 (file)
--- a/tests/anlogic/shifter.v
+++ b/tests/anlogic/shifter.v
@@ -9,14 +9,8 @@ in
 \r
     always @(posedge clk)\r
        begin\r
-`ifndef BUG\r
                out    <= out >> 1;\r
                out[7] <= in;\r
-`else\r
-\r
-               out    <= out << 1;\r
-               out[7] <= in;\r
-`endif\r
        end\r
 \r
 endmodule\r

diff --git a/tests/anlogic/tribuf.v b/tests/anlogic/tribuf.v
index 870a0258412efadf17e29e5a41dd6d49d09767a3..90dd314e4728c20accf90b5dbdc058a1a66e7490 100644 (file)
--- a/tests/anlogic/tribuf.v
+++ b/tests/anlogic/tribuf.v
@@ -6,18 +6,3 @@ module tristate (en, i, o);
        assign o = en ? i : 1'bz;
 
 endmodule
-
-
-module top (
-input en,
-input a,
-output b
-);
-
-tristate u_tri (
-        .en (en ),
-        .i (a ),
-        .o (b )
-    );
-
-endmodule

diff --git a/tests/anlogic/tribuf.ys b/tests/anlogic/tribuf.ys
index 663e93fb2a0a1a04c05caf97e33cf5bd0ac78320..0eb1338ac8d4d6a0fb16f9a191cb88035be13dba 100644 (file)
--- a/tests/anlogic/tribuf.ys
+++ b/tests/anlogic/tribuf.ys
@@ -1,9 +1,9 @@
 read_verilog tribuf.v
-hierarchy -top top
+hierarchy -top tristate
 proc
 flatten
 equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd tristate # Constrain all select calls below inside the top module
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D