gas/testsuite/

2005-05-25  Jan Beulich  <jbeulich@novell.com>

	* gas/i386/intelok.d: Account for 32-bit displacements being shown
	in hex.

opcodes/
2005-05-25  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
	hex (but retain it being displayed as signed). Remove redundant
	checks. Add handling of displacements for 16-bit addressing in Intel
	mode.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 7705ed47621b7583b88aabe70afc3499f2552ea7..14a58c3af22642ca750a9455b092a9279cc4cc9d 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2005-05-25  Jan Beulich  <jbeulich@novell.com>
+
+       * gas/i386/intelok.d: Account for 32-bit displacements being shown
+       in hex.
+
 2005-05-24  H.J. Lu  <hongjiu.lu@intel.com>
 
        * gas/elf/group0b.d: Updated.

diff --git a/gas/testsuite/gas/i386/intelok.d b/gas/testsuite/gas/i386/intelok.d
index e8a80a7b42cb7bdab130f0d85f44371fd409c130..fb84866816ed3adfc97ae9d9a7c1958aa22844f2 100644 (file)
--- a/gas/testsuite/gas/i386/intelok.d
+++ b/gas/testsuite/gas/i386/intelok.d
@@ -104,8 +104,8 @@ Disassembly of section .text:
 [      ]*[0-9a-f]+:    8b 40 0c[       ]+mov[  ]+eax,(DWORD PTR )?\[eax\+12\]
 [      ]*[0-9a-f]+:    8b 40 12[       ]+mov[  ]+eax,(DWORD PTR )?\[eax\+18\]
 [      ]*[0-9a-f]+:    8b 40 12[       ]+mov[  ]+eax,(DWORD PTR )?\[eax\+18\]
-[      ]*[0-9a-f]+:    8b 04 85 02 00 00 00[   ]+mov[  ]+eax,(DWORD PTR )?\[eax\*4\+2\]
-[      ]*[0-9a-f]+:    8b 04 85 02 00 00 00[   ]+mov[  ]+eax,(DWORD PTR )?\[eax\*4\+2\]
+[      ]*[0-9a-f]+:    8b 04 85 02 00 00 00[   ]+mov[  ]+eax,(DWORD PTR )?\[eax\*4\+(0x)?2\]
+[      ]*[0-9a-f]+:    8b 04 85 02 00 00 00[   ]+mov[  ]+eax,(DWORD PTR )?\[eax\*4\+(0x)?2\]
 [      ]*[0-9a-f]+:    8b 04 45 00 00 00 00[   ]+mov[  ]+eax,(DWORD PTR )?\[eax\*2\]
 [      ]*[0-9a-f]+:    8b 04 45 00 00 00 00[   ]+mov[  ]+eax,(DWORD PTR )?\[eax\*2\]
 [      ]*[0-9a-f]+:    8b 04 8d 00 00 00 00[   ]+mov[  ]+eax,(DWORD PTR )?\[ecx\*4\]
@@ -156,7 +156,7 @@ Disassembly of section .text:
 [      ]*[0-9a-f]+:    8b 80 00 00 00 00[      ]+mov[  ]+eax,(DWORD PTR )?\[eax\]
 [      ]*[0-9a-f]+:    8b 40 01[       ]+mov[  ]+eax,(DWORD PTR )?\[eax\+1]
 [      ]*[0-9a-f]+:    8b 80 00 00 00 00[      ]+mov[  ]+eax,(DWORD PTR )?\[eax\]
-[      ]*[0-9a-f]+:    8b 80 01 00 00 00[      ]+mov[  ]+eax,(DWORD PTR )?\[eax\+1\]
+[      ]*[0-9a-f]+:    8b 80 01 00 00 00[      ]+mov[  ]+eax,(DWORD PTR )?\[eax\+(0x)?1\]
 [      ]*[0-9a-f]+:    8b 80 00 00 00 00[      ]+mov[  ]+eax,(DWORD PTR )?\[eax\]
 [      ]*[0-9a-f]+:    8b 40 01[       ]+mov[  ]+eax,(DWORD PTR )?\[eax\+1\]
 [      ]*[0-9a-f]+:    a1 01 00 00 00[         ]+mov[  ]+eax,ds:0x1

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7b57e5b7388df2413d076022ad85510a81df69f8..6713f2d4a55580a98c1c7e99e953439116cbc44e 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2005-05-25  Jan Beulich  <jbeulich@novell.com>
+
+       * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
+       hex (but retain it being displayed as signed). Remove redundant
+       checks. Add handling of displacements for 16-bit addressing in Intel
+       mode.
+
 2005-05-25  Jan Beulich  <jbeulich@novell.com>
 
        * i386-dis.c (prefix_name): Remove pointless mode_64bit check.

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 9a8b73f48cf3da7b90912d2304d482d9047001bc..16c80b657bef948257f251583379467127410c0c 100644 (file)
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -3337,22 +3337,23 @@ OP_E (int bytemode, int sizeflag)
                  oappend (scratchbuf);
                }
            }
-         if (intel_syntax)
-           if (mod != 0 || (base & 7) == 5)
-             {
-               /* Don't print zero displacements.  */
-               if (disp != 0)
-                 {
-                   if ((bfd_signed_vma) disp > 0)
-                     {
-                       *obufp++ = '+';
-                       *obufp = '\0';
-                     }
-
-                   print_operand_value (scratchbuf, 0, disp);
-                   oappend (scratchbuf);
-                 }
-             }
+         if (intel_syntax && disp)
+           {
+             if ((bfd_signed_vma) disp > 0)
+               {
+                 *obufp++ = '+';
+                 *obufp = '\0';
+               }
+             else if (mod != 1)
+               {
+                 *obufp++ = '-';
+                 *obufp = '\0';
+                 disp = - (bfd_signed_vma) disp;
+               }
+
+             print_operand_value (scratchbuf, mod != 1, disp);
+             oappend (scratchbuf);
+           }
 
          *obufp++ = close_char;
          *obufp = '\0';
@@ -3410,10 +3411,41 @@ OP_E (int bytemode, int sizeflag)
        {
          *obufp++ = open_char;
          *obufp = '\0';
-         oappend (index16[rm + add]);
+         oappend (index16[rm]);
+         if (intel_syntax && disp)
+           {
+             if ((bfd_signed_vma) disp > 0)
+               {
+                 *obufp++ = '+';
+                 *obufp = '\0';
+               }
+             else if (mod != 1)
+               {
+                 *obufp++ = '-';
+                 *obufp = '\0';
+                 disp = - (bfd_signed_vma) disp;
+               }
+
+             print_operand_value (scratchbuf, mod != 1, disp);
+             oappend (scratchbuf);
+           }
+
          *obufp++ = close_char;
          *obufp = '\0';
        }
+      else if (intel_syntax)
+       {
+         if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
+                         | PREFIX_ES | PREFIX_FS | PREFIX_GS))
+           ;
+         else
+           {
+             oappend (names_seg[ds_reg - es_reg]);
+             oappend (":");
+           }
+         print_operand_value (scratchbuf, 1, disp & 0xffff);
+         oappend (scratchbuf);
+       }
     }
 }