begin merge of soc.vhdl, fix Makefile

diff --git a/Makefile b/Makefile
index aff1b193d1f053f71612eca4f2eea53b7620bf5e..a9a008a22beaa413a7ab4c278afb4dd51563b3de 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -210,6 +210,14 @@ OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 endif
 
+ifeq ($(FPGA_TARGET), verilator)
+RESET_LOW=true
+CLK_INPUT=50000000
+CLK_FREQUENCY=50000000
+clkgen=fpga/clk_gen_bypass.vhd
+endif
+
+
 ifneq ($(litedram_target),)
 soc_extra_synth += litedram/extras/litedram-wrapper-l2.vhdl \
        litedram/generated/$(litedram_target)/litedram-initmem.vhdl
@@ -249,9 +257,6 @@ ifeq ($(EXTERNAL_CORE),false)
                nonrandom.vhdl
 
        synth_files = $(core_files) $(soc_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
-       
-microwatt.v: $(synth_files) $(RAM_INIT_FILE)
-       $(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
 else
 #incomplete: does not build yet
     util_files = decode_types.vhdl common.vhdl wishbone_types.vhdl utils.vhdl \
@@ -259,8 +264,6 @@ else
     fpga_files = $(_fpga_files) $(_soc_files)
     synth_files = $(util_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
     soc_extra_v = external_core_top.v
-microwatt.v: $(synth_files) $(RAM_INIT_FILE) $(soc_extra_v)
-       $(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); write_verilog $@"
 endif
 #--
 
@@ -271,6 +274,9 @@ microwatt-verilator-broken: microwatt.v verilator/microwatt-verilator.cpp verila
        $(VERILATOR) $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" -Iuart16550 --assert --cc --exe --build $^ -o $@ -top-module toplevel
        @cp -f obj_dir/microwatt-verilator microwatt-verilator
        
+microwatt.v: $(synth_files) $(RAM_INIT_FILE)
+       $(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
+       
        
 #MEMORY_SIZE=16777216 # 268435456
 #RAM_INIT_FILE=dtbImage.microwatt.hex

diff --git a/soc.vhdl b/soc.vhdl
index 5f355966e0f98fe7fb804c0360b033e17be910c4..fd059b9e1027cda2f0732641084efbd2d6bcac92 100644 (file)
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -64,10 +64,15 @@ entity soc is
         HAS_BTC            : boolean := true;
         HAS_SHORT_MULT     : boolean := false;
        DISABLE_FLATTEN_CORE : boolean := false;
+       EXTERNAL_CORE : boolean := false;
         ALT_RESET_ADDRESS  : std_logic_vector(63 downto 0) := (23 downto 0 => '0', others => '1');
        HAS_DRAM           : boolean  := false;
        SIM_MAIN_BRAM      : boolean  := false;
+       --FIXME: SIM_BRAM_CHAINBOOT      : positive  := 0;
        DRAM_SIZE          : integer := 0;
+       RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
+    -- hack to jump-start alternative (e.g. verilator-loaded linux kernel)
+    -- RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (22 downto 21 => '1', others => '0');
         DRAM_INIT_SIZE     : integer := 0;
         HAS_SPI_FLASH      : boolean := false;
         SPI_FLASH_DLINES   : positive := 1;
@@ -116,7 +121,7 @@ entity soc is
         ext_irq_eth          : in std_ulogic := '0';
         ext_irq_sdcard       : in std_ulogic := '0';
 
-    -- BRAM verilator access
+    -- BRAM verilator access [FIXME]
     bram_we : out std_ulogic;
     bram_re : out std_ulogic;
     bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0);
@@ -143,14 +148,23 @@ entity soc is
         spi_flash_sdat_o  : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
         spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
         spi_flash_sdat_i  : in  std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
+        
+               -- DRAM controller signals
+               alt_reset    : in std_ulogic := '0';
+               
+                   -- for verilator debugging
+               nia_req: out std_ulogic;
+               nia: out std_ulogic_vector(63 downto 0);
+               msr_o: out std_ulogic_vector(63 downto 0);
+               insn: out std_ulogic_vector(31 downto 0);
+        ldst_req: out std_ulogic;
+        ldst_addr: out std_ulogic_vector(63 downto 0);
 
         -- GPIO signals
         gpio_out : out std_ulogic_vector(NGPIO - 1 downto 0);
         gpio_dir : out std_ulogic_vector(NGPIO - 1 downto 0);
-        gpio_in  : in  std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0');
+        gpio_in  : in  std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0')
 
-       -- DRAM controller signals
-       alt_reset    : in std_ulogic := '0'
        );
 end entity soc;
 
@@ -338,6 +352,35 @@ architecture behaviour of soc is
     end component;
 
     constant UART0_IS_POTATO : boolean := not UART0_IS_16550;
+    
+    -- use this for external processor core (e.g. mycore.v, not core.vhdl)
+    component external_core_top port (
+        clk          : in std_ulogic;
+        rst          : in std_ulogic;
+        alt_reset    : in std_ulogic;
+        wishbone_insn_in  : in wishbone_slave_out;
+        wishbone_insn_out : out wishbone_master_out;
+
+        wishbone_data_in  : in wishbone_slave_out;
+        wishbone_data_out : out wishbone_master_out;
+        dmi_addr    : in std_ulogic_vector(3 downto 0) := (others => 'U');
+        dmi_din         : in std_ulogic_vector(63 downto 0) := (others => 'U');
+        dmi_dout    : out std_ulogic_vector(63 downto 0) := (others => 'U');
+        dmi_req         : in std_ulogic := 'U';
+        dmi_wr      : in std_ulogic := 'U';
+        dmi_ack         : out std_ulogic := 'U';
+        ext_irq     : in std_ulogic;
+        terminated_out   : out std_logic := 'U';
+        -- for verilator debugging
+        nia_req: out std_ulogic := 'U';
+        msr_o: out std_ulogic_vector(63 downto 0) := (others => 'U');
+        nia: out std_ulogic_vector(63 downto 0) := (others => 'U');
+        insn: out std_ulogic_vector(31 downto 0) := (others => 'U');
+        ldst_req: out std_ulogic := 'U';
+        ldst_addr: out std_ulogic_vector(63 downto 0) := (others => 'U')
+        );
+    end component;
+    
 begin
 
     resets: process(system_clk)