ppc: support dsrd instruction

diff --git a/gas/testsuite/gas/ppc/dsrd.d b/gas/testsuite/gas/ppc/dsrd.d
new file mode 100644 (file)
index 0000000..a443818
--- /dev/null
+++ b/gas/testsuite/gas/ppc/dsrd.d
@@ -0,0 +1,16 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*:\s+(13 e0 00 36|36 00 e0 13)\s+dsrd\s+r31,r0,r0,r0
+.*:\s+(10 1f 00 36|36 00 1f 10)\s+dsrd\s+r0,r31,r0,r0
+.*:\s+(10 00 f8 36|36 f8 00 10)\s+dsrd\s+r0,r0,r31,r0
+.*:\s+(10 00 07 f6|f6 07 00 10)\s+dsrd\s+r0,r0,r0,r31
+.*:\s+(13 e0 00 37|37 00 e0 13)\s+dsrd.\s+r31,r0,r0,r0
+.*:\s+(10 1f 00 37|37 00 1f 10)\s+dsrd.\s+r0,r31,r0,r0
+.*:\s+(10 00 f8 37|37 f8 00 10)\s+dsrd.\s+r0,r0,r31,r0
+.*:\s+(10 00 07 f7|f7 07 00 10)\s+dsrd.\s+r0,r0,r0,r31

diff --git a/gas/testsuite/gas/ppc/dsrd.s b/gas/testsuite/gas/ppc/dsrd.s
new file mode 100644 (file)
index 0000000..96faf9a
--- /dev/null
+++ b/gas/testsuite/gas/ppc/dsrd.s
@@ -0,0 +1,8 @@
+dsrd 31,0,0,0
+dsrd 0,31,0,0
+dsrd 0,0,31,0
+dsrd 0,0,0,31
+dsrd. 31,0,0,0
+dsrd. 0,31,0,0
+dsrd. 0,0,31,0
+dsrd. 0,0,0,31

diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 6f41bb48b35275a896567e4924907744711c7bd4..cc4c755df1e8c6247d79911aa81a9d3f0cdf9df4 100644 (file)
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -172,3 +172,4 @@ run_dump_test "maddedu"
 run_dump_test "divmod2du"
 run_dump_test "sadd"
 run_dump_test "dsld"
+run_dump_test "dsrd"

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 7f4486a2ae47872b39e78b203aa8c8ae7e8fdf97..96037806129cfa9b27b989389ae3b1f9b467ed81 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -5216,6 +5216,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"ps_muls1",   A  (4,  13,0),  AFRB_MASK,   PPCPS,     0,              {FRT, FRA, FRC}},
 {"dsld",       VA2(4,26,0),    VA2_MASK,    SFFS,      PPCVLE,         {RT, RA, RB, RC}},
 {"dsld.",      VA2(4,26,1),    VA2_MASK,    SFFS,      PPCVLE,         {RT, RA, RB, RC}},
+{"dsrd",       VA2(4,27,0),    VA2_MASK,    SFFS,      PPCVLE,         {RT, RA, RB, RC}},
+{"dsrd.",      VA2(4,27,1),    VA2_MASK,    SFFS,      PPCVLE,         {RT, RA, RB, RC}},
 {"vextduhvrx", VX (4,  27),    VXRC_MASK,   POWER10,   0,              {VD, VA, VB, RC}},
 {"ps_muls1.",  A  (4,  13,1),  AFRB_MASK,   PPCPS,     0,              {FRT, FRA, FRC}},
 {"vextduwvlx", VX (4,  28),    VXRC_MASK,   POWER10,   0,              {VD, VA, VB, RC}},