abc9_ops: assert on $specify2 properties

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index d08c42e3b7f12ee43a2786875a4fc83bfb42bda8..52beae4212111d4d7f73893f2b170e7987ff182e 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -572,7 +572,10 @@ void prep_lut(RTLIL::Design *design, int maxlut)
                                continue;
                        log_assert(cell->getParam(ID(SRC_WIDTH)) == 1);
                        log_assert(cell->getParam(ID(DST_WIDTH)) == 1);
+                       SigBit s = cell->getPort(ID(SRC));
                        SigBit d = cell->getPort(ID(DST));
+                       log_assert(s.wire->port_input);
+                       log_assert(d.wire->port_output);
                        if (o == SigBit())
                                o = d;
                        else