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diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index 2a448fe2b494eed18b660b889881cf8f179d23c9..c674542c381f84b866f8e46bd4f337ca13100f85 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -52,7 +52,9 @@ The Mode table for Arithmetic and Logical operations
 | 00  |   1 | SVM 1   | Pack/Unpack mode, SUBVL>1   |
 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
 | 01  | inv | VLi RC1 |  Rc=0: ffirst z/nonz |
-| 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
+| 10  |   N | dz   sz |  sat mode: N=0/1 u/s, SUBVL=1 |
+| 10  |   N | zz   0  |  sat mode: N=0/1 u/s, SUBVL>1 |
+| 10  |   N | zz   1  |  Pack/Unpack sat mode: N=0/1 u/s, SUBVL>1 |
 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
 | 11  | inv | zz  RC1 |  Rc=0: pred-result z/nonz |
 
@@ -116,6 +118,10 @@ new crrweird instruction with Rc=1, which will transfer the required
 CR bits to a scalar integer and update CR0, which will allow testing
 the scalar integer for nonzero.  see [[sv/cr_int_predication]]*
 
+Pack/Unpack may be enabled at the same time as Saturation,
+when SUBVL is vec2/3/4. This provides equivalent VSX `vpkpx` and other
+operations.
+
 # Reduce mode
 
 Reduction in SVP64 is similar in essence to other Vector Processing