write_verilog: write $tribuf cell as ternary.

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 8da3c0627363b24c1736d9fada6166242253f794..54281e32ecc67c1a79a78f6ab578d30cd83488ba 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -789,6 +789,18 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
                return true;
        }
 
+       if (cell->type == "$tribuf")
+       {
+               f << stringf("%s" "assign ", indent.c_str());
+               dump_sigspec(f, cell->getPort("\\Y"));
+               f << stringf(" = ");
+               dump_sigspec(f, cell->getPort("\\EN"));
+               f << stringf(" ? ");
+               dump_sigspec(f, cell->getPort("\\A"));
+               f << stringf(" : %d'bz;\n", cell->parameters.at("\\WIDTH").as_int());
+               return true;
+       }
+
        if (cell->type == "$slice")
        {
                f << stringf("%s" "assign ", indent.c_str());