opcodes int vs bfd_boolean fixes

cpu/
	* frv.opc (frv_is_branch_major, frv_is_float_major),
	(frv_is_media_major, frv_is_branch_insn, frv_is_float_insn),
	(frv_is_media_insn, spr_valid): Correct prototypes.
include/
	* opcode/aarch64.h (aarch64_opcode_encode): Correct prototype.
opcodes/
	* arc-dis.c (extract_operand_value): Correct NULL cast.
	* frv-opc.h: Regenerate.

diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index 638450610afd7e1fdee9f6bd7190fc1daacb3800..1684d2611190a5442cc92e3bf8e166119c76d83c 100644 (file)
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,9 @@
+2021-03-29  Alan Modra  <amodra@gmail.com>
+
+       * frv.opc (frv_is_branch_major, frv_is_float_major),
+       (frv_is_media_major, frv_is_branch_insn, frv_is_float_insn),
+       (frv_is_media_insn, spr_valid): Correct prototypes.
+
 2021-01-09  Nick Clifton  <nickc@redhat.com>
 
        * 2.36 release branch crated.

diff --git a/cpu/frv.opc b/cpu/frv.opc
index 1b0b05c29a061cb1d33076aed7e3893cc1179d6d..7863462dafe63c2369529381d06cb713441396ec 100644 (file)
--- a/cpu/frv.opc
+++ b/cpu/frv.opc
@@ -66,15 +66,15 @@ typedef struct
   const CGEN_INSN *      insn[FRV_VLIW_SIZE];
 } FRV_VLIW;
 
-int frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-int frv_is_float_major  (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-int frv_is_media_major  (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-int frv_is_branch_insn  (const CGEN_INSN *);
-int frv_is_float_insn   (const CGEN_INSN *);
-int frv_is_media_insn   (const CGEN_INSN *);
-void frv_vliw_reset     (FRV_VLIW *, unsigned long, unsigned long);
-int frv_vliw_add_insn   (FRV_VLIW *, const CGEN_INSN *);
-int spr_valid           (long);
+bfd_boolean frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bfd_boolean frv_is_float_major  (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bfd_boolean frv_is_media_major  (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bfd_boolean frv_is_branch_insn  (const CGEN_INSN *);
+bfd_boolean frv_is_float_insn   (const CGEN_INSN *);
+bfd_boolean frv_is_media_insn   (const CGEN_INSN *);
+void        frv_vliw_reset      (FRV_VLIW *, unsigned long, unsigned long);
+int         frv_vliw_add_insn   (FRV_VLIW *, const CGEN_INSN *);
+bfd_boolean spr_valid           (long);
 /* -- */
 \f
 /* -- opc.c */

diff --git a/include/ChangeLog b/include/ChangeLog
index 5fa6b09ac846831f0858b0574d4c7918812a9014..afc1ac95c1f745d241d2b064a7c5a36d58a040bb 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2021-03-29  Alan Modra  <amodra@gmail.com>
+
+       * opcode/aarch64.h (aarch64_opcode_encode): Correct prototype.
+
 2021-03-25  Nick Alcock  <nick.alcock@oracle.com>
 
        PR libctf/27628

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index f99869103108283451c660d9bc149dda8b6b1d41..dd4ab22f9aef2c114b28f073c1497c6772ec14c0 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1264,7 +1264,7 @@ struct aarch64_instr_sequence
 
 /* Encoding entrypoint.  */
 
-extern int
+extern bfd_boolean
 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
                       aarch64_insn *, aarch64_opnd_qualifier_t *,
                       aarch64_operand_error *, aarch64_instr_sequence *);

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0e2e94c111c7d11c80c555b97952900f4ea8ff32..7a531b36a7bf7a94b8753a00ddb7066189db62f1 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2021-03-29  Alan Modra  <amodra@gmail.com>
+
+       * arc-dis.c (extract_operand_value): Correct NULL cast.
+       * frv-opc.h: Regenerate.
+
 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 
        * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to

diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 0c9b379bd2b7bf5741be495cc900673d9b434245..a7e2db151a07e539cb4a1fcd0237799acb5088f4 100644 (file)
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -694,7 +694,7 @@ extract_operand_value (const struct arc_operand *operand,
   else
     {
       if (operand->extract)
-        value = (*operand->extract) (insn, (int *) NULL);
+       value = (*operand->extract) (insn, (bfd_boolean *) NULL);
       else
         {
           if (operand->flags & ARC_OPERAND_ALIGNED32)

diff --git a/opcodes/frv-opc.h b/opcodes/frv-opc.h
index 9fc69222dbe02fb1940b60c5ae8067c7415cb474..95f47974c2a3646819512b7f2a8ba01c16ab8042 100644 (file)
--- a/opcodes/frv-opc.h
+++ b/opcodes/frv-opc.h
@@ -58,15 +58,15 @@ typedef struct
   const CGEN_INSN *      insn[FRV_VLIW_SIZE];
 } FRV_VLIW;
 
-int frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-int frv_is_float_major  (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-int frv_is_media_major  (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
-int frv_is_branch_insn  (const CGEN_INSN *);
-int frv_is_float_insn   (const CGEN_INSN *);
-int frv_is_media_insn   (const CGEN_INSN *);
-void frv_vliw_reset     (FRV_VLIW *, unsigned long, unsigned long);
-int frv_vliw_add_insn   (FRV_VLIW *, const CGEN_INSN *);
-int spr_valid           (long);
+bfd_boolean frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bfd_boolean frv_is_float_major  (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bfd_boolean frv_is_media_major  (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
+bfd_boolean frv_is_branch_insn  (const CGEN_INSN *);
+bfd_boolean frv_is_float_insn   (const CGEN_INSN *);
+bfd_boolean frv_is_media_insn   (const CGEN_INSN *);
+void        frv_vliw_reset      (FRV_VLIW *, unsigned long, unsigned long);
+int         frv_vliw_add_insn   (FRV_VLIW *, const CGEN_INSN *);
+bfd_boolean spr_valid           (long);
 /* -- */
 /* Enum declaration for frv instruction types.  */
 typedef enum cgen_insn_type {