radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, rmesa->radeonScreen->texSize[0]);
radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, rmesa->radeonScreen->gartTextures.size);
} else {
- struct drm_radeon_gem_info mminfo;
+ struct drm_radeon_gem_info mminfo = { 0 };
if (!drmCommandWriteRead(rmesa->dri.fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo)))
{
radeonGetParam(__DRIscreenPrivate *sPriv, int param, void *value)
{
int ret;
- drm_radeon_getparam_t gp;
- struct drm_radeon_info info;
+ drm_radeon_getparam_t gp = { 0 };
+ struct drm_radeon_info info = { 0 };
if (sPriv->drm_version.major >= 2) {
info.value = (uint64_t)value;
__driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
return NULL;
}
-
+
if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
screen->gartTextures.handle = dri_priv->gartTexHandle;
screen->gartTextures.size = dri_priv->gartTexMapSize;
__driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
return NULL;
}
-
+
screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
}
}
radeonScreenPtr screen;
int i;
int ret;
- uint32_t device_id;
+ uint32_t device_id = 0;
uint32_t temp = 0;
/* Allocate the private area */