clarify

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 7017060fd6fc3594f45d2617814f63b44bd638cc..5a9beecc9e7ee75e7ec4b18f6b3eb5d866c79142 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -445,7 +445,7 @@ def get\_pred\_val(bool is\_fp\_op, int reg):
   \end{itemize}
   Notes:\vspace{10pt}
    \begin{itemize}
-   \item Same notes apply (previous slide) as for predication CSR table
+   \item References different (internal) mapping table for INT or FP
    \item Level of indirection has implications for pipeline latency
   \end{itemize}
 }