intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY

diff --git a/techlibs/intel_alm/common/abc9_map.v b/techlibs/intel_alm/common/abc9_map.v
index 32ad79bdcc738a5f730bdcc8ce69ee523004dc66..9d11bb24093383cda8c41db5d086922fe9e1db29 100644 (file)
--- a/techlibs/intel_alm/common/abc9_map.v
+++ b/techlibs/intel_alm/common/abc9_map.v
@@ -11,7 +11,7 @@ parameter _TECHMAP_CONSTMSK_ACLR_ = 1'b0;
 
 // If the async-clear is constant, we assume it's disabled.
 if (_TECHMAP_CONSTMSK_ACLR_ != 1'b0)
-    MISTRAL_FF_SYNCONLY _TECHMAP_REPLACE_ (.DATAIN(DATAIN), .CLK(CLK), .ENA(ENA), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q));
+    $__MISTRAL_FF_SYNCONLY _TECHMAP_REPLACE_ (.DATAIN(DATAIN), .CLK(CLK), .ENA(ENA), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q));
 else
     wire _TECHMAP_FAIL_ = 1;
 

diff --git a/techlibs/intel_alm/common/abc9_model.v b/techlibs/intel_alm/common/abc9_model.v
index dd46147a5c7c5c03d7a36fd10d28a78b6319a7bf..8ad52e13ac01d0298060c9711b3381b1ef4325d9 100644 (file)
--- a/techlibs/intel_alm/common/abc9_model.v
+++ b/techlibs/intel_alm/common/abc9_model.v
@@ -18,7 +18,7 @@
 
 // This is a purely-synchronous flop, that ABC9 can use for sequential synthesis.
 (* abc9_flop, lib_whitebox *)
-module MISTRAL_FF_SYNCONLY(
+module $__MISTRAL_FF_SYNCONLY (
     input DATAIN, CLK, ENA, SCLR, SLOAD, SDATA,
     output reg Q
 );

diff --git a/techlibs/intel_alm/common/abc9_unmap.v b/techlibs/intel_alm/common/abc9_unmap.v
index 0eda69560cfd524b9f150e875f35adbeed1d8570..4b28866a3a6f1b3c9181201a768d5c81d9567162 100644 (file)
--- a/techlibs/intel_alm/common/abc9_unmap.v
+++ b/techlibs/intel_alm/common/abc9_unmap.v
@@ -1,7 +1,7 @@
 // After performing sequential synthesis, map the synchronous flops back to
 // standard MISTRAL_FF flops.
 
-module MISTRAL_FF_SYNCONLY(
+module $__MISTRAL_FF_SYNCONLY (
     input DATAIN, CLK, ENA, SCLR, SLOAD, SDATA,
     output reg Q
 );

diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc
index 982857dd587fe88b0ce877b86dde03efbde7d581..4bc943cb26609c2ee327c609bde59f984b40b32b 100644 (file)
--- a/techlibs/intel_alm/synth_intel_alm.cc
+++ b/techlibs/intel_alm/synth_intel_alm.cc
@@ -173,7 +173,7 @@ struct SynthIntelALMPass : public ScriptPass {
                        run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt.c_str()));
                        run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str()));
                        run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt.c_str()));
-                       run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/abc9_model.v", family_opt.c_str()));
+                       run(stringf("read_verilog -specify -lib -D %s -icells +/intel_alm/common/abc9_model.v", family_opt.c_str()));
 
                        // Misc and common cells
                        run("read_verilog -lib +/intel/common/altpll_bb.v");