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authorlkcl <lkcl@web>
Fri, 9 Mar 2018 13:35:37 +0000 (13:35 +0000)
committerIkiWiki <ikiwiki.info>
Fri, 9 Mar 2018 13:35:37 +0000 (13:35 +0000)
shakti/m_class/wishbone.mdwn patch | blob | history

diff --git a/shakti/m_class/wishbone.mdwn b/shakti/m_class/wishbone.mdwn
index e623b71fd6ae5218ae574c13dead90a659d8a3af..6748b9f8e4b0136dee8ca538d82366fbea9346b5 100644 (file)
--- a/shakti/m_class/wishbone.mdwn
+++ b/shakti/m_class/wishbone.mdwn
@@ -1,5 +1,7 @@
 # Wishbone Bridge
 
 See also [[AXI]] Bus
+
 * <http://bugs.libre-riscv.org/show_bug.cgi?id=11>
 * <https://github.com/alexforencich/verilog-wishbone>
+* <https://github.com/albertxie/iverilog-tutorial.git>
http://libre-riscv.org ikiwiki