Improve ice40_dsp for non-fully-32-bit adders

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index e0a213e85b579ced1e9ff8a03f8ff584bdae2ae2..c59c5d20ad7f8d612adc650da866724916e2baf1 100644 (file)
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -106,7 +106,9 @@ endcode
 match addA
        select addA->type.in($add)
        select nusers(port(addA, \A)) == 2
-       index <SigSpec> port(addA, \A) === sigH
+       filter param(addA, \A_WIDTH).as_int() <= GetSize(sigH)
+       //index <SigSpec> port(addA, \A) === sigH.extract(0, param(addA, \A_WIDTH).as_int())
+       filter port(addA, \A) ==  sigH.extract(0, param(addA, \A_WIDTH).as_int())
        optional
 endmatch
 
@@ -114,7 +116,9 @@ match addB
        if !addA
        select addB->type.in($add, $sub)
        select nusers(port(addB, \B)) == 2
-       index <SigSpec> port(addB, \B) === sigH
+       filter param(addB, \B_WIDTH).as_int() <= GetSize(sigH)
+       //index <SigSpec> port(addB, \B) === sigH.extract(0, param(addB, \B_WIDTH).as_int())
+       filter port(addB, \B) ==  sigH.extract(0, param(addB, \B_WIDTH).as_int())
        optional
 endmatch
 
@@ -144,7 +148,8 @@ code addAB sigCD sigO
 
                if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
                        reject;
-               if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
+               // If accumulator, check adder width and signedness
+               if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
                        reject;
 
                sigO = port(addAB, \Y);