Update long regression stats for semi-recent cache changes.

--HG--
extra : convert_revision : 7fef1e4f684ced37479ed363ebbb3a7485bc0d52

diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index 60a97b97b9136cd1c0957e2527498c06a378fce0..595b91bdc0ad3a1dbe2194d53b87118dcd060b80 100644 (file)
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -376,6 +376,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 

diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt
index 04959f23f70b9f5245b05525c99890f69e9b95d2..ca33458cbdf83317fc64de5c89bf3dd0b290d596 100644 (file)
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                4205990                       # Nu
 global.BPredUnit.condPredicted               70175548                       # Number of conditional branches predicted
 global.BPredUnit.lookups                     76112488                       # Number of BP lookups
 global.BPredUnit.usedRAS                      1692573                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 185893                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 223968                       # Number of bytes of host memory used
-host_seconds                                  3042.35                       # Real time elapsed on the host
-host_tick_rate                               54375513                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 131337                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 179084                       # Number of bytes of host memory used
+host_seconds                                  4306.11                       # Real time elapsed on the host
+host_tick_rate                               38417331                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads           21896719                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores          16284345                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads             127086189                       # Number of loads inserted to the mem dependence unit.
@@ -53,61 +53,61 @@ system.cpu.cpi                               0.585019                       # CP
 system.cpu.cpi_total                         0.585019                       # CPI: Total CPI of All Threads
 system.cpu.dcache.LoadLockedReq_accesses            1                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_hits                1                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses          114321557                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 26993.890628                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses          115038352                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency  6257.587595                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency  3367.177206                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              114105250                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_miss_latency     5838967500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.001892                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               216307                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_miss_rate          0.008111                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses               933102                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_mshr_hits            716795                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_miss_latency    728344000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001892                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001880                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses          216307                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses          37579282                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 48790.597140                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_accesses          39451321                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency  7448.640662                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency  7159.473367                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits              37241994                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_latency   16456482928                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.008975                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              337288                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_miss_rate         0.056001                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             2209327                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_mshr_hits          1872039                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_miss_latency   2414804453                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.008975                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.008549                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses         337288                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs  1999.750000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets         2750                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 320.196392                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                 321.245700                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  4                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets                4                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs         7999                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_targets        11000                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           151900839                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 40273.937496                       # average overall miss latency
+system.cpu.dcache.demand_accesses           154489673                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency  7094.973483                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency  5677.703832                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits               151347244                       # number of demand (read+write) hits
 system.cpu.dcache.demand_miss_latency     22295450428                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.003644                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                553595                       # number of demand (read+write) misses
+system.cpu.dcache.demand_miss_rate           0.020341                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               3142429                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits            2588834                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_miss_latency   3143148453                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.003644                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.003583                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses           553595                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses          151900839                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 40273.937496                       # average overall miss latency
+system.cpu.dcache.overall_accesses          154489673                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency  7094.973483                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency  5677.703832                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits              151347244                       # number of overall hits
 system.cpu.dcache.overall_miss_latency    22295450428                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.003644                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               553595                       # number of overall misses
+system.cpu.dcache.overall_miss_rate          0.020341                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              3142429                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits           2588834                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_miss_latency   3143148453                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.003644                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.003583                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses          553595                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -124,7 +124,7 @@ system.cpu.dcache.replacements                 468826                       # nu
 system.cpu.dcache.sampled_refs                 472922                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.tagsinuse               4095.170465                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                151427918                       # Total number of references to valid blocks.
+system.cpu.dcache.total_refs                151924159                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               50285000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   334126                       # number of writebacks
 system.cpu.decode.DECODE:BlockedCycles       46422286                       # Number of cycles decode is blocked
@@ -173,13 +173,13 @@ system.cpu.fetch.rateDist.min_value                 0
 system.cpu.fetch.rateDist.max_value                 8                      
 system.cpu.fetch.rateDist.end_dist
 
-system.cpu.icache.ReadReq_accesses           66025546                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 10641.352550                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_accesses           66025670                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency  9355.263158                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency  6819.290466                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits               66024644                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency        9598500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000014                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  902                       # number of ReadReq misses
+system.cpu.icache.ReadReq_miss_rate          0.000016                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                 1026                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_hits               124                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_miss_latency      6151000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000014                       # mshr miss rate for ReadReq accesses
@@ -192,13 +192,13 @@ system.cpu.icache.blocked_no_targets                0                       # nu
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            66025546                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 10641.352550                       # average overall miss latency
+system.cpu.icache.demand_accesses            66025670                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency  9355.263158                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency  6819.290466                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                66024644                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency         9598500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000014                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   902                       # number of demand (read+write) misses
+system.cpu.icache.demand_miss_rate           0.000016                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                  1026                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                124                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_miss_latency      6151000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000014                       # mshr miss rate for demand accesses
@@ -206,14 +206,14 @@ system.cpu.icache.demand_mshr_misses              902                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses           66025546                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 10641.352550                       # average overall miss latency
+system.cpu.icache.overall_accesses           66025670                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency  9355.263158                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency  6819.290466                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits               66024644                       # number of overall hits
 system.cpu.icache.overall_miss_latency        9598500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000014                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  902                       # number of overall misses
+system.cpu.icache.overall_miss_rate          0.000016                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                 1026                       # number of overall misses
 system.cpu.icache.overall_mshr_hits               124                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_miss_latency      6151000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000014                       # mshr miss rate for overall accesses

diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr
index 598fc86c01d808d65a74c80f0575e9015aa3be5c..8053728f79f4df460e25df9e8b10c19068bed439 100644 (file)
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr
@@ -1,3 +1,3 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7006
+0: system.remote_gdb.listener: listening for remote gdb on port 7001
 warn: Entering event queue @ 0.  Starting simulation...
 warn: Increasing stack size by one page.

diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
index 857d77efe25aeec56452ce19f7fe3a6fb42bd845..4e87924caecae476d857b17c16879681a3aa3253 100644 (file)
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -376,6 +376,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 

diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
index a32e8681ee6bd3ead50ae29b30b2ca4b023bf6c3..623095a720ce0967e29bea8e2f879cd8f2ce33d0 100644 (file)
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect               84375502                       # Nu
 global.BPredUnit.condPredicted              253548806                       # Number of conditional branches predicted
 global.BPredUnit.lookups                    253548806                       # Number of BP lookups
 global.BPredUnit.usedRAS                            0                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 116576                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 226608                       # Number of bytes of host memory used
-host_seconds                                 12057.44                       # Real time elapsed on the host
-host_tick_rate                               91455071                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  60603                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 181372                       # Number of bytes of host memory used
+host_seconds                                 23193.76                       # Real time elapsed on the host
+host_tick_rate                               47543564                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads          445533165                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores         138523488                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads             741821167                       # Number of loads inserted to the mem dependence unit.
@@ -51,16 +51,16 @@ system.cpu.committedInsts                  1405610550                       # Nu
 system.cpu.committedInsts_total            1405610550                       # Number of Instructions Simulated
 system.cpu.cpi                               1.569018                       # CPI: Cycles Per Instruction
 system.cpu.cpi_total                         1.569018                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses          430903803                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 21506.820895                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses          431513840                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency  5832.966573                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2978.823732                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              430676780                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_miss_latency     4882543000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.000527                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               227023                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_miss_rate          0.001940                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses               837060                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_mshr_hits            610037                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_miss_latency    676261500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000527                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000526                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses          227023                       # number of ReadReq MSHR misses
 system.cpu.dcache.SwapReq_accesses               1326                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_avg_miss_latency  9037.500000                       # average SwapReq miss latency
@@ -72,50 +72,50 @@ system.cpu.dcache.SwapReq_misses                   40                       # nu
 system.cpu.dcache.SwapReq_mshr_miss_latency       241500                       # number of SwapReq MSHR miss cycles
 system.cpu.dcache.SwapReq_mshr_miss_rate     0.030166                       # mshr miss rate for SwapReq accesses
 system.cpu.dcache.SwapReq_mshr_misses              40                       # number of SwapReq MSHR misses
-system.cpu.dcache.WriteReq_accesses         165064291                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 64362.786896                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_accesses         166856456                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 10313.606533                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency  7754.204206                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits             164722312                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_latency   22010721500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.002072                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              341979                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_miss_rate         0.012790                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             2134144                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_mshr_hits          1792165                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_miss_latency   2651775000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.002072                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.002050                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses         341979                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                1192.736607                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                1192.980326                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           595968094                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 47263.919107                       # average overall miss latency
+system.cpu.dcache.demand_accesses           598370296                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency  9051.301930                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency  5848.901234                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits               595399092                       # number of demand (read+write) hits
 system.cpu.dcache.demand_miss_latency     26893264500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000955                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                569002                       # number of demand (read+write) misses
+system.cpu.dcache.demand_miss_rate           0.004965                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               2971204                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits            2402202                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_miss_latency   3328036500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.000955                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000951                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses           569002                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses          595968094                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 47263.919107                       # average overall miss latency
+system.cpu.dcache.overall_accesses          598370296                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency  9051.301930                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency  5848.901234                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits              595399092                       # number of overall hits
 system.cpu.dcache.overall_miss_latency    26893264500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000955                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               569002                       # number of overall misses
+system.cpu.dcache.overall_miss_rate          0.004965                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              2971204                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits           2402202                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_miss_latency   3328036500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.000955                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000951                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses          569002                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -132,7 +132,7 @@ system.cpu.dcache.replacements                 495151                       # nu
 system.cpu.dcache.sampled_refs                 499247                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.tagsinuse               4095.753267                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                595470173                       # Total number of references to valid blocks.
+system.cpu.dcache.total_refs                595591849                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               85544000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   338813                       # number of writebacks
 system.cpu.decode.DECODE:BlockedCycles      411958316                       # Number of cycles decode is blocked
@@ -166,13 +166,13 @@ system.cpu.fetch.rateDist.min_value                 0
 system.cpu.fetch.rateDist.max_value                 8                      
 system.cpu.fetch.rateDist.end_dist
 
-system.cpu.icache.ReadReq_accesses          356679310                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  9956.762749                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_accesses          356679455                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency  8992.990654                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency  6465.262380                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits              356677957                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency       13471500                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000004                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 1353                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses                 1498                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_hits               145                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_miss_latency      8747500                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000004                       # mshr miss rate for ReadReq accesses
@@ -185,13 +185,13 @@ system.cpu.icache.blocked_no_targets                0                       # nu
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           356679310                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  9956.762749                       # average overall miss latency
+system.cpu.icache.demand_accesses           356679455                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency  8992.990654                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency  6465.262380                       # average overall mshr miss latency
 system.cpu.icache.demand_hits               356677957                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency        13471500                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000004                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  1353                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses                  1498                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                145                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_miss_latency      8747500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000004                       # mshr miss rate for demand accesses
@@ -199,14 +199,14 @@ system.cpu.icache.demand_mshr_misses             1353                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses          356679310                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  9956.762749                       # average overall miss latency
+system.cpu.icache.overall_accesses          356679455                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency  8992.990654                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency  6465.262380                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits              356677957                       # number of overall hits
 system.cpu.icache.overall_miss_latency       13471500                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000004                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 1353                       # number of overall misses
+system.cpu.icache.overall_misses                 1498                       # number of overall misses
 system.cpu.icache.overall_mshr_hits               145                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_miss_latency      8747500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000004                       # mshr miss rate for overall accesses

diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
index 8ee292d5b9b284ec4cc79371897b1c21d52d679b..d3d1e3cfb236ff9477ad57fff7e8c5ddab0beea9 100644 (file)
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
@@ -36,9 +36,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 24 2008 13:27:50
-M5 started Mon Feb 25 16:16:45 2008
-M5 executing on tater
+M5 compiled Mar 17 2008 06:14:16
+M5 started Mon Mar 17 06:14:18 2008
+M5 executing on zizzer
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 1102714100000 because target called exit()

diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 50eaa3f41e0fb237617644a9511d61c75aa7c712..56c9263b33f9cfb49ab87df38eeed95097f78185 100644 (file)
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -376,6 +376,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 

diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt
index 3af370c7d7aae056035c90cce9da060c25c047c1..c2cc5eeb49f0d56da4efa9fdcedbf276a052d8e3 100644 (file)
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                5691744                       # Nu
 global.BPredUnit.condPredicted               35558640                       # Number of conditional branches predicted
 global.BPredUnit.lookups                     62480259                       # Number of BP lookups
 global.BPredUnit.usedRAS                     12398507                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 155119                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 205336                       # Number of bytes of host memory used
-host_seconds                                  2421.21                       # Real time elapsed on the host
-host_tick_rate                               55712012                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  99164                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 157680                       # Number of bytes of host memory used
+host_seconds                                  3787.43                       # Real time elapsed on the host
+host_tick_rate                               35615266                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads           72769124                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores          54049353                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads             125306666                       # Number of loads inserted to the mem dependence unit.
@@ -53,43 +53,43 @@ system.cpu.cpi                               0.718313                       # CP
 system.cpu.cpi_total                         0.718313                       # CPI: Total CPI of All Threads
 system.cpu.dcache.LoadLockedReq_accesses            1                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_hits                1                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses           95885180                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 15194.726166                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses           95885716                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency  9843.626807                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7312.880325                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               95884194                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_miss_latency       14982000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.000010                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                  986                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_miss_rate          0.000016                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses                 1522                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_mshr_hits               536                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_miss_latency      7210500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses             986                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses          73513083                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 32019.486405                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_accesses          73520729                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency  9673.649142                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency  7598.791541                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits              73509773                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_latency     105984500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000045                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                3310                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_miss_rate         0.000149                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses               10956                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_mshr_hits             7646                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_miss_latency     25152000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000045                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses           3310                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               40554.006943                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs               40554.032799                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           169398263                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 28157.937616                       # average overall miss latency
+system.cpu.dcache.demand_accesses           169406445                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency  9694.382113                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency  7533.170391                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits               169393967                       # number of demand (read+write) hits
 system.cpu.dcache.demand_miss_latency       120966500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  4296                       # number of demand (read+write) misses
+system.cpu.dcache.demand_miss_rate           0.000074                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                 12478                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits               8182                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_miss_latency     32362500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
@@ -97,14 +97,14 @@ system.cpu.dcache.demand_mshr_misses             4296                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses          169398263                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 28157.937616                       # average overall miss latency
+system.cpu.dcache.overall_accesses          169406445                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency  9694.382113                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency  7533.170391                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits              169393967                       # number of overall hits
 system.cpu.dcache.overall_miss_latency      120966500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 4296                       # number of overall misses
+system.cpu.dcache.overall_miss_rate          0.000074                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                12478                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits              8182                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_miss_latency     32362500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
@@ -124,7 +124,7 @@ system.cpu.dcache.replacements                    781                       # nu
 system.cpu.dcache.sampled_refs                   4177                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.tagsinuse               3296.858616                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                169394087                       # Total number of references to valid blocks.
+system.cpu.dcache.total_refs                169394195                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                      636                       # number of writebacks
 system.cpu.decode.DECODE:BlockedCycles       18955564                       # Number of cycles decode is blocked
@@ -173,13 +173,13 @@ system.cpu.fetch.rateDist.min_value                 0
 system.cpu.fetch.rateDist.max_value                 8                      
 system.cpu.fetch.rateDist.end_dist
 
-system.cpu.icache.ReadReq_accesses           64020369                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  9431.835687                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_accesses           64020665                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency  8765.688380                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency  6021.951220                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits               64016474                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency       36737000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000061                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 3895                       # number of ReadReq misses
+system.cpu.icache.ReadReq_miss_rate          0.000065                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                 4191                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_hits               296                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_miss_latency     23455500                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000061                       # mshr miss rate for ReadReq accesses
@@ -192,13 +192,13 @@ system.cpu.icache.blocked_no_targets                0                       # nu
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            64020369                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  9431.835687                       # average overall miss latency
+system.cpu.icache.demand_accesses            64020665                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency  8765.688380                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency  6021.951220                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                64016474                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency        36737000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000061                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  3895                       # number of demand (read+write) misses
+system.cpu.icache.demand_miss_rate           0.000065                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                  4191                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                296                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_miss_latency     23455500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000061                       # mshr miss rate for demand accesses
@@ -206,14 +206,14 @@ system.cpu.icache.demand_mshr_misses             3895                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses           64020369                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  9431.835687                       # average overall miss latency
+system.cpu.icache.overall_accesses           64020665                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency  8765.688380                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency  6021.951220                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits               64016474                       # number of overall hits
 system.cpu.icache.overall_miss_latency       36737000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000061                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 3895                       # number of overall misses
+system.cpu.icache.overall_miss_rate          0.000065                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                 4191                       # number of overall misses
 system.cpu.icache.overall_mshr_hits               296                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_miss_latency     23455500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000061                       # mshr miss rate for overall accesses

diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index fcea1b6562eb8013174044fcc27437c386e24e1a..78b7f1eec52a2c88efd40923fd665438c2d656d2 100644 (file)
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -376,6 +376,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 

diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt
index 3829dd79982ad4e4b25f7fe6590eabdcc5c2a785..2e39bfe337bbdcb0ebbdca544581e7380e0eea41 100644 (file)
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                 455745                       # Nu
 global.BPredUnit.condPredicted               10549276                       # Number of conditional branches predicted
 global.BPredUnit.lookups                     16239906                       # Number of BP lookups
 global.BPredUnit.usedRAS                      1939086                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 101925                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 220292                       # Number of bytes of host memory used
-host_seconds                                   780.89                       # Real time elapsed on the host
-host_tick_rate                               32150232                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 108698                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 171788                       # Number of bytes of host memory used
+host_seconds                                   732.23                       # Real time elapsed on the host
+host_tick_rate                               34286652                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads           12312682                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores          10887004                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads              22965315                       # Number of loads inserted to the mem dependence unit.
@@ -53,61 +53,61 @@ system.cpu.cpi                               0.630861                       # CP
 system.cpu.cpi_total                         0.630861                       # CPI: Total CPI of All Threads
 system.cpu.dcache.LoadLockedReq_accesses           44                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_hits               44                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses           20369036                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 19244.510005                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses           20452895                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency  8143.771495                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency  4564.311373                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               20307515                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_miss_latency     1183941500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.003020                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                61521                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_miss_rate          0.007108                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses               145380                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_mshr_hits             83859                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_miss_latency    280801000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.003020                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.003008                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses           61521                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses          13753160                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 50456.177120                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_accesses          14613377                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency  7484.182742                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency  7344.479005                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits              13603341                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_latency    7559294000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.010893                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              149819                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_miss_rate         0.069117                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             1010036                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_mshr_hits           860217                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_miss_latency   1100342500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.010893                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.010252                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses         149819                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 165.441832                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                 165.460856                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            34122196                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 41370.471752                       # average overall miss latency
+system.cpu.dcache.demand_accesses            35066272                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency  7567.175372                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency  6535.173181                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                33910856                       # number of demand (read+write) hits
 system.cpu.dcache.demand_miss_latency      8743235500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.006194                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                211340                       # number of demand (read+write) misses
+system.cpu.dcache.demand_miss_rate           0.032949                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               1155416                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits             944076                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_miss_latency   1381143500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.006194                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.006027                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses           211340                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses           34122196                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 41370.471752                       # average overall miss latency
+system.cpu.dcache.overall_accesses           35066272                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency  7567.175372                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency  6535.173181                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits               33910856                       # number of overall hits
 system.cpu.dcache.overall_miss_latency     8743235500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.006194                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               211340                       # number of overall misses
+system.cpu.dcache.overall_miss_rate          0.032949                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              1155416                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits            944076                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_miss_latency   1381143500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.006194                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.006027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses          211340                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -124,7 +124,7 @@ system.cpu.dcache.replacements                 200914                       # nu
 system.cpu.dcache.sampled_refs                 205010                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.tagsinuse               4080.749840                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 33917230                       # Total number of references to valid blocks.
+system.cpu.dcache.total_refs                 33921130                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              125269000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   147756                       # number of writebacks
 system.cpu.decode.DECODE:BlockedCycles        1159763                       # Number of cycles decode is blocked
@@ -173,16 +173,16 @@ system.cpu.fetch.rateDist.min_value                 0
 system.cpu.fetch.rateDist.max_value                 8                      
 system.cpu.fetch.rateDist.end_dist
 
-system.cpu.icache.ReadReq_accesses           13372459                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  5833.169458                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_accesses           13373612                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency  5755.491777                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency  2760.964989                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits               13287028                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency      498333500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.006389                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                85431                       # number of ReadReq misses
+system.cpu.icache.ReadReq_miss_rate          0.006474                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                86584                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_hits              1153                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_miss_latency    235872000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.006389                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate     0.006388                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses           85431                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
@@ -192,31 +192,31 @@ system.cpu.icache.blocked_no_targets                0                       # nu
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            13372459                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  5833.169458                       # average overall miss latency
+system.cpu.icache.demand_accesses            13373612                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency  5755.491777                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency  2760.964989                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                13287028                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency       498333500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.006389                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 85431                       # number of demand (read+write) misses
+system.cpu.icache.demand_miss_rate           0.006474                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                 86584                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits               1153                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_miss_latency    235872000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.006389                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate      0.006388                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses            85431                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses           13372459                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  5833.169458                       # average overall miss latency
+system.cpu.icache.overall_accesses           13373612                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency  5755.491777                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency  2760.964989                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits               13287028                       # number of overall hits
 system.cpu.icache.overall_miss_latency      498333500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.006389                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                85431                       # number of overall misses
+system.cpu.icache.overall_miss_rate          0.006474                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                86584                       # number of overall misses
 system.cpu.icache.overall_mshr_hits              1153                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_miss_latency    235872000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.006389                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate     0.006388                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses           85431                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses

diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr
index 8053728f79f4df460e25df9e8b10c19068bed439..5992f7131175e9d9b95fd6a3c87ae2b8bf145469 100644 (file)
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr
@@ -1,3 +1,3 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7001
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
 warn: Entering event queue @ 0.  Starting simulation...
 warn: Increasing stack size by one page.

diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index 966f49abc0a30607f12cd9fb20d953738c8e4a1e..abff97de4f49c3d91a901317a1137dd493a07541 100644 (file)
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -376,6 +376,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 

diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
index d545db1117da2aec4cd26809c287062188d42e9e..98a4ae9ba7abc4009b916c4fab929a866622a156 100644 (file)
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect               19461333                       # Nu
 global.BPredUnit.condPredicted              256954278                       # Number of conditional branches predicted
 global.BPredUnit.lookups                    332748805                       # Number of BP lookups
 global.BPredUnit.usedRAS                     23332154                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 185907                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 374916                       # Number of bytes of host memory used
-host_seconds                                  9338.25                       # Real time elapsed on the host
-host_tick_rate                               70823738                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  98561                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 329172                       # Number of bytes of host memory used
+host_seconds                                 17613.94                       # Real time elapsed on the host
+host_tick_rate                               37548074                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads           73213571                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores          37308198                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads             599919223                       # Number of loads inserted to the mem dependence unit.
@@ -61,61 +61,61 @@ system.cpu.dcache.LoadLockedReq_misses              1                       # nu
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency         6500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.333333                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_misses            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses          513272040                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  8025.908244                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses          514699566                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency  6709.313547                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency  3665.501336                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              505997425                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_miss_latency    58385392500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.014173                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              7274615                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_miss_rate          0.016907                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses              8702141                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_mshr_hits           1427526                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_miss_latency  26665111000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.014173                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.014134                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses         7274615                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses         158750545                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 19340.801620                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 10289.713687                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10117.659004                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits             156501908                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_latency   43490442133                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.014165                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             2248637                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_miss_rate         0.026296                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             4226594                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_mshr_hits          1977957                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_miss_latency  22750942389                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.014165                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.013990                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses        2248637                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs  2040.681665                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets  2667.920935                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  72.369821                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  72.404790                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs              71409                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets            65111                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs    145723037                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_targets    173711000                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           672022585                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 10697.588873                       # average overall miss latency
+system.cpu.dcache.demand_accesses           675428068                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency  7879.799117                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency  5188.989369                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits               662499333                       # number of demand (read+write) hits
 system.cpu.dcache.demand_miss_latency    101875834633                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.014171                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               9523252                       # number of demand (read+write) misses
+system.cpu.dcache.demand_miss_rate           0.019142                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses              12928735                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits            3405483                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_miss_latency  49416053389                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.014171                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.014100                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses          9523252                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses          672022585                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 10697.588873                       # average overall miss latency
+system.cpu.dcache.overall_accesses          675428068                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency  7879.799117                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency  5188.989369                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits              662499333                       # number of overall hits
 system.cpu.dcache.overall_miss_latency   101875834633                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.014171                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              9523252                       # number of overall misses
+system.cpu.dcache.overall_miss_rate          0.019142                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses             12928735                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits           3405483                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_miss_latency  49416053389                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.014171                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.014100                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses         9523252                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -132,7 +132,7 @@ system.cpu.dcache.replacements                9155291                       # nu
 system.cpu.dcache.sampled_refs                9159387                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.tagsinuse               4084.377148                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                662863201                       # Total number of references to valid blocks.
+system.cpu.dcache.total_refs                663183492                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             6956358000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                  2245548                       # number of writebacks
 system.cpu.decode.DECODE:BlockedCycles       25695554                       # Number of cycles decode is blocked
@@ -181,13 +181,13 @@ system.cpu.fetch.rateDist.min_value                 0
 system.cpu.fetch.rateDist.max_value                 8                      
 system.cpu.fetch.rateDist.end_dist
 
-system.cpu.icache.ReadReq_accesses          340572130                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 10589.900111                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_accesses          340572268                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency  9183.349374                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency  6758.046615                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits              340571229                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency        9541500                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000003                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  901                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses                 1039                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_hits               138                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_miss_latency      6089000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000003                       # mshr miss rate for ReadReq accesses
@@ -200,13 +200,13 @@ system.cpu.icache.blocked_no_targets                0                       # nu
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           340572130                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 10589.900111                       # average overall miss latency
+system.cpu.icache.demand_accesses           340572268                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency  9183.349374                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency  6758.046615                       # average overall mshr miss latency
 system.cpu.icache.demand_hits               340571229                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency         9541500                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000003                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   901                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses                  1039                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                138                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_miss_latency      6089000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000003                       # mshr miss rate for demand accesses
@@ -214,14 +214,14 @@ system.cpu.icache.demand_mshr_misses              901                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses          340572130                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 10589.900111                       # average overall miss latency
+system.cpu.icache.overall_accesses          340572268                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency  9183.349374                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency  6758.046615                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits              340571229                       # number of overall hits
 system.cpu.icache.overall_miss_latency        9541500                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000003                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  901                       # number of overall misses
+system.cpu.icache.overall_misses                 1039                       # number of overall misses
 system.cpu.icache.overall_mshr_hits               138                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_miss_latency      6089000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000003                       # mshr miss rate for overall accesses

diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index a81a73367bafebb4bdbc2f3fe3cd4254c1abd737..945804e3d557dc650826f54c52f014a1e3b8b357 100644 (file)
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -376,6 +376,7 @@ max_stack_size=67108864
 output=cout
 pid=100
 ppid=99
+simpoint=0
 system=system
 uid=100
 

diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
index 2580b06c82845213f33e1b0d3aa7fec3458496f8..4231c8e95a9fe15b825acdcf67c707370018fb60 100644 (file)
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                1950052                       # Nu
 global.BPredUnit.condPredicted               14577615                       # Number of conditional branches predicted
 global.BPredUnit.lookups                     19451761                       # Number of BP lookups
 global.BPredUnit.usedRAS                      1721600                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  79678                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 202860                       # Number of bytes of host memory used
-host_seconds                                  1056.50                       # Real time elapsed on the host
-host_tick_rate                               38578826                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  82033                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 156240                       # Number of bytes of host memory used
+host_seconds                                  1026.17                       # Real time elapsed on the host
+host_tick_rate                               39719192                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads           17804625                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores           5077040                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads              33854360                       # Number of loads inserted to the mem dependence unit.
@@ -53,43 +53,43 @@ system.cpu.cpi                               0.968368                       # CP
 system.cpu.cpi_total                         0.968368                       # CPI: Total CPI of All Threads
 system.cpu.dcache.LoadLockedReq_accesses            7                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_hits                7                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses           23270992                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 11553.149606                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses           23271115                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency  9301.109350                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency  6675.196850                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               23270484                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_miss_latency        5869000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.000022                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                  508                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_miss_rate          0.000027                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses                  631                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_mshr_hits               123                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_miss_latency      3391000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses             508                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses           6494911                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 34394.822006                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency  7925.428784                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency  7197.950378                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits               6493057                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_latency      63768000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000285                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                1854                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_miss_rate         0.001238                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                8046                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_mshr_hits             6192                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_miss_latency     13345000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000285                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses           1854                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               13269.579581                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs               13269.627731                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            29765903                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 29482.218459                       # average overall miss latency
+system.cpu.dcache.demand_accesses            29772218                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency  8025.469632                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency  7085.520745                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                29763541                       # number of demand (read+write) hits
 system.cpu.dcache.demand_miss_latency        69637000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000079                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  2362                       # number of demand (read+write) misses
+system.cpu.dcache.demand_miss_rate           0.000291                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                  8677                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits               6315                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_miss_latency     16736000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000079                       # mshr miss rate for demand accesses
@@ -97,14 +97,14 @@ system.cpu.dcache.demand_mshr_misses             2362                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses           29765903                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 29482.218459                       # average overall miss latency
+system.cpu.dcache.overall_accesses           29772218                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency  8025.469632                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency  7085.520745                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits               29763541                       # number of overall hits
 system.cpu.dcache.overall_miss_latency       69637000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000079                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 2362                       # number of overall misses
+system.cpu.dcache.overall_miss_rate          0.000291                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                 8677                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits              6315                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_miss_latency     16736000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000079                       # mshr miss rate for overall accesses
@@ -124,7 +124,7 @@ system.cpu.dcache.replacements                    159                       # nu
 system.cpu.dcache.sampled_refs                   2243                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.tagsinuse               1461.984287                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 29763667                       # Total number of references to valid blocks.
+system.cpu.dcache.total_refs                 29763775                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                      105                       # number of writebacks
 system.cpu.decode.DECODE:BlockedCycles        3862301                       # Number of cycles decode is blocked
@@ -173,13 +173,13 @@ system.cpu.fetch.rateDist.min_value                 0
 system.cpu.fetch.rateDist.max_value                 8                      
 system.cpu.fetch.rateDist.end_dist
 
-system.cpu.icache.ReadReq_accesses           19219343                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  6740.447436                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_accesses           19219800                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency  6448.716735                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency  3507.077806                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits               19209241                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency       68092000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000526                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                10102                       # number of ReadReq misses
+system.cpu.icache.ReadReq_miss_rate          0.000549                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                10559                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_hits               457                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_miss_latency     35428500                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000526                       # mshr miss rate for ReadReq accesses
@@ -192,13 +192,13 @@ system.cpu.icache.blocked_no_targets                0                       # nu
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            19219343                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  6740.447436                       # average overall miss latency
+system.cpu.icache.demand_accesses            19219800                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency  6448.716735                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency  3507.077806                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                19209241                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency        68092000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000526                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 10102                       # number of demand (read+write) misses
+system.cpu.icache.demand_miss_rate           0.000549                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                 10559                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                457                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_miss_latency     35428500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000526                       # mshr miss rate for demand accesses
@@ -206,14 +206,14 @@ system.cpu.icache.demand_mshr_misses            10102                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses           19219343                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  6740.447436                       # average overall miss latency
+system.cpu.icache.overall_accesses           19219800                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency  6448.716735                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency  3507.077806                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits               19209241                       # number of overall hits
 system.cpu.icache.overall_miss_latency       68092000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000526                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                10102                       # number of overall misses
+system.cpu.icache.overall_miss_rate          0.000549                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                10559                       # number of overall misses
 system.cpu.icache.overall_mshr_hits               457                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_miss_latency     35428500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000526                       # mshr miss rate for overall accesses