Add dynamic slicing Verilog testcase

diff --git a/tests/simple/dynslice.v b/tests/simple/dynslice.v
new file mode 100644 (file)
index 0000000..7236ac3
--- /dev/null
+++ b/tests/simple/dynslice.v
@@ -0,0 +1,12 @@
+module dynslice (
+    input clk ,
+    input [9:0] ctrl ,
+    input [15:0] din ,
+    input [3:0] sel ,
+    output reg [127:0] dout
+);
+always @(posedge clk)
+begin
+    dout[ctrl*sel+:16] <= din ;
+end
+endmodule