[ARC] Fix LE tests for nps400 variant.

gcc/arc: New peephole2 and little endian arc test fixes

Resolve some test failures introduced for little endian arc as a result
of the recent arc/nps400 additions.

There's a new peephole2 optimisation to merge together two zero_extracts
in order that the movb instruction can be used.

One of the test cases is extended so that the test does something
meaningful in both big and little endian arc mode.

Other tests have their expected results updated to reflect improvements
in other areas of GCC.

gcc/ChangeLog:

 Andrew Burgess  <andrew.burgess@embecosm.com>

	* config/arc/arc.md (movb peephole2): New peephole2 to merge two
	zero_extract operations to allow a movb to occur.
	* gcc.target/arc/movb-1.c: Update little endian arc results.
	* gcc.target/arc/movb-2.c: Likewise.
	* gcc.target/arc/movb-5.c: Likewise.
	* gcc.target/arc/movh_cl-1.c: Extend test to cover little endian
	arc.

From-SVN: r242484

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a9263afaef24272bc68c7802efeb184a2f48ea94..40922a098fb15398ff64b6187e2c5848822d50ea 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2016-11-16  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * config/arc/arc.md (movb peephole2): New peephole2 to merge two
+       zero_extract operations to allow a movb to occur.
+       * testsuite/gcc.target/arc/movb-1.c: Update little endian arc results.
+       * testsuite/gcc.target/arc/movb-2.c: Likewise.
+       * testsuite/gcc.target/arc/movb-5.c: Likewise.
+       * testsuite/gcc.target/arc/movh_cl-1.c: Extend test to cover
+       little endian arc.
+
 2016-11-16  Richard Sandiford  <richard.sandiford@arm.com>
            Alan Hayward  <alan.hayward@arm.com>
            David Sherwood  <david.sherwood@arm.com>

diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 429611e4a30d284621dcb318c1504e536cef7f93..c494ca5dc604f62b5172f7469cf2cbb3ef984a4d 100644 (file)
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -6225,6 +6225,20 @@
    (set_attr "iscompact" "maybe,false")
    (set_attr "predicable" "no,no")])
 
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand" "")
+       (zero_extract:SI (match_dup 0)
+                        (match_operand:SI 1 "const_int_operand" "")
+                        (match_operand:SI 2 "const_int_operand" "")))
+   (set (zero_extract:SI (match_operand:SI 3 "register_operand" "")
+                        (match_dup 1)
+                        (match_dup 2))
+       (match_dup 0))]
+  "TARGET_NPS_BITOPS
+   && !reg_overlap_mentioned_p (operands[0], operands[3])"
+  [(set (zero_extract:SI (match_dup 3) (match_dup 1) (match_dup 2))
+       (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2)))])
+
 ;; include the arc-FPX instructions
 (include "fpx.md")
 

diff --git a/gcc/testsuite/gcc.target/arc/movb-1.c b/gcc/testsuite/gcc.target/arc/movb-1.c
index 65d4ba4b6ab4d55635b6d26eae0c908e76cab715..94d9f5fcd5e99da369ee037f1ae38485cc788d6c 100644 (file)
--- a/gcc/testsuite/gcc.target/arc/movb-1.c
+++ b/gcc/testsuite/gcc.target/arc/movb-1.c
@@ -10,4 +10,4 @@ f (void)
   bar.b = foo.b;
 }
 /* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *5, *3, *8" { target arceb-*-* } } } */
-/* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *19, *21, *8" { target arc-*-* } } } */
+/* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *3, *5, *8" { target arc-*-* } } } */

diff --git a/gcc/testsuite/gcc.target/arc/movb-2.c b/gcc/testsuite/gcc.target/arc/movb-2.c
index 1ba9976a566d7f0cc69e39aa832d0c986f8b40e2..708f393497dc724c26921aa626989b8e5a59f3d7 100644 (file)
--- a/gcc/testsuite/gcc.target/arc/movb-2.c
+++ b/gcc/testsuite/gcc.target/arc/movb-2.c
@@ -9,5 +9,5 @@ f (void)
 {
   bar.b = foo.b;
 }
-/* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *23, *23, *9" { target arc-*-* } } } */
+/* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *7, *7, *9" { target arc-*-* } } } */
 /* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *0, *0, *9" { target arceb-*-* } } } */

diff --git a/gcc/testsuite/gcc.target/arc/movb-5.c b/gcc/testsuite/gcc.target/arc/movb-5.c
index 9dbe8a1e09a887a4b0bfb20f61d1a3732b6dc35a..d28588807820212c053fef45cc8fd413d807d4b7 100644 (file)
--- a/gcc/testsuite/gcc.target/arc/movb-5.c
+++ b/gcc/testsuite/gcc.target/arc/movb-5.c
@@ -9,5 +9,5 @@ f (void)
 {
   bar.b = foo.b;
 }
-/* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *23, *(23|7), *9" { target arc-*-* } } } */
+/* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *7, *7, *9" { target arc-*-* } } } */
 /* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *0, *0, *9" { target arceb-*-* } } } */

diff --git a/gcc/testsuite/gcc.target/arc/movh_cl-1.c b/gcc/testsuite/gcc.target/arc/movh_cl-1.c
index 220cd9d72b94bc447438341573507436cbfd0465..c6434811e8afd3096ec988c486a759523df1a32d 100644 (file)
--- a/gcc/testsuite/gcc.target/arc/movh_cl-1.c
+++ b/gcc/testsuite/gcc.target/arc/movh_cl-1.c
@@ -10,6 +10,9 @@ struct thing
     {
       unsigned a : 1;
       unsigned b : 1;
+      unsigned c : 28;
+      unsigned d : 1;
+      unsigned e : 1;
     };
   };
 };
@@ -24,4 +27,12 @@ blah ()
   func (xx.raw);
 }
 
+void
+woof ()
+{
+  struct thing xx;
+  xx.d = xx.e = 1;
+  func (xx.raw);
+}
+
 /* { dg-final { scan-assembler "movh\.cl r\[0-9\]+,0xc0000000>>16" } } */