Fix building with yosys/nextpnr

Add --no-formal so that asserts are removed by yosys as nextpnr
doesn't like them.

This was suggested by @tgingold here:
  https://github.com/YosysHQ/yosys/issues/2068#issuecomment-644545863

Signed-off-by: Michael Neuling <mikey@neuling.org>

diff --git a/Makefile b/Makefile
index 96631e77ab71c139f179de7732f280473e3a41c8..b4dab318d3c47b6b644cf6d7a9b22b1121ee0f76 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -175,10 +175,10 @@ fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \
 synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 
 microwatt.json: $(synth_files)
-       $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@"
+       $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@"
 
 microwatt.v: $(synth_files)
-       $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
+       $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
 
 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c