/* HardPFResp */
{ SET4(IsRead, IsResponse, IsHWPrefetch, HasData),
InvalidCmd, "HardPFResp" },
- /* WriteInvalidateReq */
+ /* WriteInvalidateReq (currently unused, see packet.hh) */
{ SET6(IsWrite, NeedsExclusive, IsInvalidate,
IsRequest, HasData, NeedsResponse),
WriteInvalidateResp, "WriteInvalidateReq" },
- /* WriteInvalidateResp */
+ /* WriteInvalidateResp (currently unused, see packet.hh) */
{ SET3(IsWrite, NeedsExclusive, IsResponse),
InvalidCmd, "WriteInvalidateResp" },
/* UpgradeReq */
HardPFReq,
SoftPFResp,
HardPFResp,
+ // WriteInvalidateReq transactions used to be generated by the
+ // DMA ports when writing full blocks to memory, however, it
+ // is not used anymore since we put the I/O cache in place to
+ // deal with partial block writes. Hence, WriteInvalidateReq
+ // and WriteInvalidateResp are currently unused. The
+ // implication is that the I/O cache does read-exclusive
+ // operations on every full-cache-block DMA, and ultimately
+ // this needs to be fixed.
WriteInvalidateReq,
WriteInvalidateResp,
UpgradeReq,
IsRead, //!< Data flows from responder to requester
IsWrite, //!< Data flows from requester to responder
IsUpgrade,
- IsPrefetch, //!< Not a demand access
IsInvalidate,
NeedsExclusive, //!< Requires exclusive copy to complete in-cache
IsRequest, //!< Issued by requester