i965/cnl: Add l3 configuration for Cannonlake

V2 (Anuj):
Squash the changes in one patch rebase on master.
Address the review comments made by Francisco Jerez.
Do the URB allocation per slice (not per bank).

V3 (Anuj):
Update the comment.
Format the table as other l3 config tables.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
---
V1 was sent out with the heading:
"i965/cnl: Properly handle l3 configuration"

diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index 21ee5ca5dcae7d7c2d3ab098ee634039c7419ea7..aff13c06ec0f83800ed1c94ef1bcfbdc333919b4 100644 (file)
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -115,6 +115,23 @@ static const struct gen_l3_config bxt_2x6_l3_configs[] = {
    {{ 0 }}
 };
 
+/**
+ * CNL validated L3 configurations.  \sa ivb_l3_configs.
+ */
+static const struct gen_l3_config cnl_l3_configs[] = {
+   /* SLM URB ALL DC  RO  IS   C   T */
+   {{  0, 64, 64,  0,  0,  0,  0,  0 }},
+   {{  0, 64,  0, 16, 48,  0,  0,  0 }},
+   {{  0, 48,  0, 16, 64,  0,  0,  0 }},
+   {{  0, 32,  0,  0, 96,  0,  0,  0 }},
+   {{  0, 32, 96,  0,  0,  0,  0,  0 }},
+   {{  0, 32,  0, 16, 80,  0,  0,  0 }},
+   {{ 32, 16, 80,  0,  0,  0,  0,  0 }},
+   {{ 32, 16,  0, 64, 16,  0,  0,  0 }},
+   {{ 32,  0, 96,  0,  0,  0,  0,  0 }},
+   {{ 0 }}
+};
+
 /**
  * Return a zero-terminated array of validated L3 configurations for the
  * specified device.
@@ -130,11 +147,13 @@ get_l3_configs(const struct gen_device_info *devinfo)
       return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
 
    case 9:
-   case 10:
       if (devinfo->l3_banks == 1)
          return bxt_2x6_l3_configs;
       return chv_l3_configs;
 
+   case 10:
+      return cnl_l3_configs;
+
    default:
       unreachable("Not implemented");
    }