xilinx/common: be sure language is not vhdl when yosys synthesis is used

diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py
index 9ddc165e0797cf9ffe31487f46a228aa4aac95aa..1b3f052baa030e43a5a4a28fc21176065d95610e 100644 (file)
--- a/litex/build/xilinx/common.py
+++ b/litex/build/xilinx/common.py
@@ -241,6 +241,7 @@ def _run_yosys(device, sources, vincpaths, build_name):
     for path in vincpaths:
         incflags += " -I" + path
     for filename, language, library in sources:
+        assert language != "vhdl"
         ys_contents += "read_{}{} {}\n".format(language, incflags, filename)
 
     ys_contents += """\