Add cells.lut to techlibs/xilinx/
authorEddie Hung <eddie@fpgeh.com>
Tue, 9 Apr 2019 21:33:37 +0000 (14:33 -0700)
committerEddie Hung <eddie@fpgeh.com>
Tue, 9 Apr 2019 21:33:37 +0000 (14:33 -0700)
techlibs/xilinx/Makefile.inc
techlibs/xilinx/cells.lut [new file with mode: 0644]

index 9937c0c9cd8ff7c397cd249b7d6475f391bbb495..432bb0770ae85ee3bdec257fcab32f740fa8e8ee 100644 (file)
@@ -31,6 +31,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.lut))
 
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
diff --git a/techlibs/xilinx/cells.lut b/techlibs/xilinx/cells.lut
new file mode 100644 (file)
index 0000000..3f3b69a
--- /dev/null
@@ -0,0 +1,15 @@
+# Max delays from https://pastebin.com/v2hrcksd 
+# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
+
+# Since LUT delays are pushed onto the fabric as routing delays,
+# assume each input costs +100ps
+
+# K    area    delay
+1      11      224
+2      12      224 324
+3      13      224 324 424
+4      14      224 324 424 524
+5      15      224 324 424 524 624
+6      20      224 324 424 524 624 724
+7      40      224 324 424 524 624 724 1020
+8      80      224 324 424 524 624 724 1020 1293