add sv.bc/vs - VLset - test. truncates VL at the vector-condition-fail point

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 40fcdd448f66a6c6405472d5709d8dd2b0d792dd..ef98f04f671bec0919f3f88eeedcc4955d7b2de1 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -37,7 +37,7 @@ from openpower.decoder.power_enums import SVPtype
 from openpower.decoder.helpers import (exts, gtu, ltu, undefined,
                                        ISACallerHelper, ISAFPHelpers)
 from openpower.consts import PIb, MSRb  # big-endian (PowerISA versions)
-from openpower.consts import (SVP64MODE,
+from openpower.consts import (SVP64MODE, SVP64MODEb,
                               SVP64CROffs,
                               )
 from openpower.decoder.power_svp64 import SVP64RM, decode_extra
@@ -1220,13 +1220,15 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         if self.is_svp64_mode and insn_name.startswith("sv.bc"):
             # blegh grab bits manually
             mode = yield self.dec2.rm_dec.rm_in.mode
-            bc_vlset = (mode & SVP64MODE.BC_VLSET) != 0
-            bc_vli = (mode & SVP64MODE.BC_VLI) != 0
-            bc_snz = (mode & SVP64MODE.BC_SNZ) != 0
+            mode = SelectableInt(mode, 5) # convert to SelectableInt before test
+            bc_vlset = mode[SVP64MODEb.BC_VLSET] != 0
+            bc_vli = mode[SVP64MODEb.BC_VLI] != 0
+            bc_snz = mode[SVP64MODEb.BC_SNZ] != 0
             bc_vsb = yield self.dec2.rm_dec.bc_vsb
             bc_lru = yield self.dec2.rm_dec.bc_lru
             bc_gate = yield self.dec2.rm_dec.bc_gate
             sz = yield self.dec2.rm_dec.pred_sz
+            self.namespace['mode'] = SelectableInt(mode, 5)
             self.namespace['ALL'] = SelectableInt(bc_gate, 1)
             self.namespace['VSb'] = SelectableInt(bc_vsb, 1)
             self.namespace['LRu'] = SelectableInt(bc_lru, 1)

diff --git a/src/openpower/decoder/isa/test_caller_svp64_bc.py b/src/openpower/decoder/isa/test_caller_svp64_bc.py
index fef5d2f5ef6e4950ba098a124fbb79434881199e..94adc6e536484386d0c9c8964afdefaf8e8eb273 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_bc.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_bc.py
@@ -104,6 +104,36 @@ class DecoderTestCase(FHDLTestCase):
                 else:
                     self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
 
+    def test_sv_branch_cond_all_vlset(self):
+        for i in [7, 8, 9]:
+            lst = SVP64Asm(
+                [f"addi 1, 0, {i+1}",  # set r1 to i
+                 f"addi 2, 0, {i}",  # set r2 to i
+                "cmpi cr0, 1, 1, 8",  # compare r1 with 10 and store to cr0
+                "cmpi cr1, 1, 2, 8",  # compare r2 with 10 and store to cr1
+                "sv.bc/all/vs 12, *1, 0xc", # bgt 0xc - branch if BOTH
+                                       # r1 AND r2 greater 8 to the nop below
+                                       # also truncate VL at the fail-point
+                "addi 3, 0, 0x1234",   # if tests fail this shouldn't execute
+                "or 0, 0, 0"]          # branch target
+                )
+            lst = list(lst)
+
+            # SVSTATE (in this case, VL=2)
+            svstate = SVP64State()
+            svstate.vl = 2 # VL
+            svstate.maxvl = 2 # MAXVL
+            print ("SVSTATE", bin(svstate.asint()))
+
+            with Program(lst, bigendian=False) as program:
+                sim = self.run_tst_program(program, svstate=svstate)
+                if i == 9:
+                    self.assertEqual(sim.gpr(3), SelectableInt(0, 64))
+                else:
+                    self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
+                print ("SVSTATE.vl", bin(svstate.vl))
+                self.assertEqual(svstate.vl, i-7)
+
     def test_sv_branch_ctr(self):
         """XXX under development, seems to be good.
         basically this will reduce CTR under a *vector* loop, where BO[0]
@@ -145,7 +175,7 @@ class DecoderTestCase(FHDLTestCase):
     def test_sv_branch_ctr_loop(self):
         """this is a branch-ctr-loop demo which shows an (unconditional)
         decrementing of CTR by VL.  BI still has to be set to Vector even
-        though it is unused (BO[0]=1)
+        though it is unused (BO[0]=1).
         """
         maxvl = 4
         lst = SVP64Asm(
@@ -175,7 +205,7 @@ class DecoderTestCase(FHDLTestCase):
             # MAXVL repeatedly subtracted from VL (r1), last loop has remainder
             self.assertEqual(sim.gpr(1), SelectableInt(target % maxvl, 64))
 
-    def test_sv_add_cr(self):
+    def tst_sv_add_cr(self):
         """>>> lst = ['sv.add. *1, *5, *9'
                        ]