soc/cores/cpu: add add_sources static method

When creating SoC with multiple sub-SoC already generated, we need an
easy way to add cpu sources.

diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index 03d99efcc85be07134230cf054175f22f2044bfb..2ab62c7867791338b37341ccaf24d83867293e31 100644 (file)
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -56,6 +56,10 @@ class LM32(Module):
         ]
 
         # add verilog sources
+        self.add_sources(platform)
+
+    @staticmethod
+    def add_sources(platform):
         vdir = os.path.join(
             os.path.abspath(os.path.dirname(__file__)), "verilog")
         platform.add_sources(os.path.join(vdir, "submodule", "rtl"),

diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index f607d044d3320dc6138d52c26a246ee335f431f5..8ce397dbd8ad1a6def69adbaf2382738a61c9600 100644 (file)
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -105,6 +105,10 @@ class MOR1KX(Module):
         ]
 
         # add verilog sources
+        self.add_sources(platform)
+
+    @staticmethod
+    def add_sources(platform):
         vdir = os.path.join(
             os.path.abspath(os.path.dirname(__file__)),
             "verilog", "rtl", "verilog")

diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index dbce1c6412490f360d1ba793fd09dac6d0dfe0d9..ace7ee93ae14f44d3c866a8ec6092e970eece7bb 100644 (file)
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -118,6 +118,10 @@ class PicoRV32(Module):
         ]
 
         # add verilog sources
+        self.add_sources(platform)
+
+    @staticmethod
+    def add_sources(platform):
         vdir = os.path.join(
             os.path.abspath(os.path.dirname(__file__)), "verilog")
         platform.add_source(os.path.join(vdir, "picorv32.v"))

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 68aea9dde8b11fff6f4b5c256c7eb6004bab87bb..d9434742d12053805e8bc9d395d1882275ad960d 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -44,7 +44,11 @@ class VexRiscv(Module):
                                   i_dBusWishbone_ACK=d.ack,
                                   i_dBusWishbone_ERR=d.err)
 
-        # add Verilog sources
+        # add verilog sources
+        self.add_sources(platform)
+
+    @staticmethod
+    def add_sources(platform):
         vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
         platform.add_sources(os.path.join(vdir), "VexRiscv.v")
         platform.add_verilog_include_path(vdir)