add state and bank sv csr bitfields

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 66a11fde32739bc7eaa13746ca55465fdedd251e..622b829f7165a6835af4d6eedb8767ad80b14522 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -413,12 +413,18 @@ void processor_t::set_csr(int which, reg_t val)
       fprintf(stderr, "set MVL %lx\n", state.sv().mvl);
       break;
     case CSR_USVSTATE:
+    {
       // bits 0-5: mvl - 6-11: vl - 12-17: srcoffs - 18-23: destoffs
-      set_csr(CSR_USVMVL, get_field(val, 0x1f   )+1);
-      set_csr(CSR_USVVL , get_field(val, 0x1f<<6)+1);
-      state.sv().srcoffs  = std::min(get_field(val, 0x1f<<12), state.sv().vl-1);
-      state.sv().destoffs = std::min(get_field(val, 0x1f<<18), state.sv().vl-1);
+      set_csr(CSR_USVMVL, get_field(val, SV_STATE_VL )+1);
+      set_csr(CSR_USVVL , get_field(val, SV_STATE_MVL)+1);
+      reg_t srcoffs = get_field(val, SV_STATE_SRCOFFS);
+      reg_t destoffs = get_field(val, SV_STATE_DESTOFFS);
+      state.sv().srcoffs  = std::min(srcoffs , state.sv().vl-1);
+      state.sv().destoffs = std::min(destoffs, state.sv().vl-1);
+      state.sv().state_bank = get_field(val, SV_STATE_BANK);
+      state.sv().state_size = get_field(val, SV_STATE_SIZE);
       break;
+    }
     case CSR_USVVL:
       state.sv().vl = std::min(state.sv().mvl, val);
       // TODO XXX throw exception if val == 0
@@ -805,7 +811,8 @@ reg_t processor_t::get_csr(int which)
       return state.sv().vl;
     case CSR_USVSTATE:
       return (state.sv().vl-1)            | ((state.sv().mvl-1)<<6) |
-             (state.sv().srcoffs<<12)     | (state.sv().destoffs<<18) ;
+             (state.sv().srcoffs<<12)     | (state.sv().destoffs<<18) |
+             (state.sv().state_bank<<24)  | (state.sv().state_size<<26);
     case CSR_USVMVL:
       return state.sv().mvl;
     case CSR_SVREGCFG0:

diff --git a/riscv/processor.h b/riscv/processor.h
index 4e8cd3b047f3deaf1b3ca54d3df5ce8da8945160..ee37e2cb2e08802bbe7535a64e215be08f740fa6 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -95,6 +95,8 @@ typedef struct
   uint64_t mvl;
   int destoffs; // destination loop element offset
   int srcoffs;  // source loop element offset (used in twin-predication)
+  int state_size;
+  int state_bank;
   sv_reg_csr_entry sv_csrs[SV_UCSR_SZ];
   sv_reg_entry     sv_int_tb[NXPR];
   sv_reg_entry     sv_fp_tb[NFPR];

diff --git a/riscv/sv.h b/riscv/sv.h
index fc06de1d0f9a4d4972a26af0d9dea71dc1757471..b82eeecc03303b1b7dd07c7d936e4273bcfcbcaf 100644 (file)
--- a/riscv/sv.h
+++ b/riscv/sv.h
@@ -104,4 +104,11 @@ typedef struct {
 #define SV_SHAPE_PERM_ZXY 4
 #define SV_SHAPE_PERM_ZYX 5
 
+#define SV_STATE_VL (0x1f)
+#define SV_STATE_MVL (0x1f<<6)
+#define SV_STATE_SRCOFFS (0x1f<<12)
+#define SV_STATE_DESTOFFS (0x1f<<18)
+#define SV_STATE_BANK (0x1f<<24)
+#define SV_STATE_SIZE (0x1f<<26)
+
 #endif