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diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 18c8d0319980446a586ef25ed1ba0894d55b8394..f9008ab8190ac66e33ff738f59ebc5e91e128e93 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -79,9 +79,7 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 | 6 | 7 | 19-20 |  21 | 22   23 |  description     |
 | - | - |-------| --- |---------|----------------- |
 |sz |SNZ| 0 RG  |   0 | dz  /   | simple mode                      |
-|sz |SNZ| 0 RG  |   1 | 0   /   | scalar reduce mode (mapreduce), SUBVL=1 |
-|zz |SNZ| 0 RG  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
-|zz |SNZ| 0 RG  |   1 | /   1   | reserved   |
+|sz |SNZ| 0 RG  |   1 | 0   /   | scalar reduce mode (mapreduce) |
 |zz |SNZ| 1 VLI | inv |  CR-bit | Ffirst 3-bit mode      |
 |sz |SNZ| 1 VLI | inv |  dz /   | Ffirst 5-bit mode       |