targets: replace MiniSoC with EthernetSoC

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index aeda2f901fba9bc2a4b85d3080ea49016f0b5c4e..d8f3f8242ef82f9d7e7eac61ad1476e658f4e452 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -114,7 +114,7 @@ class BaseSoC(SoCSDRAM):
                             sdram_module.timing_settings)
 
 
-class MiniSoC(BaseSoC):
+class EthernetSoC(BaseSoC):
     csr_map = {
         "ethphy": 18,
         "ethmac": 19
@@ -161,7 +161,7 @@ def main():
                         help="enable Ethernet support")
     args = parser.parse_args()
 
-    cls = MiniSoC if args.with_ethernet else BaseSoC
+    cls = EthernetSoC if args.with_ethernet else BaseSoC
     soc = cls(**soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 5702a5e23fb89fdb6efc6b29b73145a10c69994f..3046ec4cf3f82308f84127f4519d1912db79daf4 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -96,7 +96,7 @@ class BaseSoC(SoCSDRAM):
                             sdram_module.timing_settings)
 
 
-class MiniSoC(BaseSoC):
+class EthernetSoC(BaseSoC):
     csr_map = {
         "ethphy": 18,
         "ethmac": 19
@@ -143,7 +143,7 @@ def main():
                         help="enable Ethernet support")
     args = parser.parse_args()
 
-    cls = MiniSoC if args.with_ethernet else BaseSoC
+    cls = EthernetSoC if args.with_ethernet else BaseSoC
     soc = cls(**soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index c2d2553d6b1009d6ea64080ea5463ebd5734615f..65730af53837d0e36701328fdb316994cfe9087b 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -96,7 +96,7 @@ class BaseSoC(SoCSDRAM):
                             sdram_module.timing_settings)
 
 
-class MiniSoC(BaseSoC):
+class EthernetSoC(BaseSoC):
     csr_map = {
         "ethphy": 18,
         "ethmac": 19
@@ -143,7 +143,7 @@ def main():
                         help="enable Ethernet support")
     args = parser.parse_args()
 
-    cls = MiniSoC if args.with_ethernet else BaseSoC
+    cls = EthernetSoC if args.with_ethernet else BaseSoC
     soc = cls(**soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 1af07c7f8eb31e323f45a21d4ec439ee3528599c..4f297deb17f41c41f346cf5bb08523142d9bc9c5 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -103,7 +103,7 @@ class BaseSoC(SoCSDRAM):
                             sdram_module.timing_settings)
 
 
-class MiniSoC(BaseSoC):
+class EthernetSoC(BaseSoC):
     csr_map = {
         "ethphy": 18,
         "ethmac": 19
@@ -150,7 +150,7 @@ def main():
                         help="enable Ethernet support")
     args = parser.parse_args()
 
-    cls = MiniSoC if args.with_ethernet else BaseSoC
+    cls = EthernetSoC if args.with_ethernet else BaseSoC
     soc = cls(**soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()

diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py
index 8577a04a1c4a1b645f524b5b91c9b3fe7a837123..de7cc60d80cffaef563e2752c589274f03468b78 100755 (executable)
--- a/litex/boards/targets/simple.py
+++ b/litex/boards/targets/simple.py
@@ -22,7 +22,7 @@ class BaseSoC(SoCCore):
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
 
-class MiniSoC(BaseSoC):
+class EthernetSoC(BaseSoC):
     csr_map = {
         "ethphy": 20,
         "ethmac": 21
@@ -62,7 +62,7 @@ def main():
 
     platform_module = importlib.import_module(args.platform)
     platform = platform_module.Platform()
-    cls = MiniSoC if args.with_ethernet else BaseSoC
+    cls = EthernetSoC if args.with_ethernet else BaseSoC
     soc = cls(platform, **soc_core_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()