cpu/vexriscv: bump submodule

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
index 03f7f9d46c9c862e1ef3ebbe19b5113b882e4358..747a2e012f43d13c3487acc3c758477aad277559 160000 (submodule)
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -1 +1 @@
-Subproject commit 03f7f9d46c9c862e1ef3ebbe19b5113b882e4358
+Subproject commit 747a2e012f43d13c3487acc3c758477aad277559